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[[File:Cmmp.jpg|thumb|350px|right|The C.mmp memory unit, with three racks visible, including the front panel of the crossbar switch.]]
The '''C.mmp''' was an early ''multiple instruction, multiple data'' ([[Multiple instruction, multiple data|MIMD]]) [[Multiprocessing|multiprocessor]] system developed at [[Carnegie Mellon University]] (CMU) by [[William Wulf]] (1971). The notation ''C.mmp'' came from the PMS notation of [[Gordon Bell]] and [[Allen Newell]],<ref>{{Cite book |last=Bell |first=C. Gordon |author-link=Gordon Bell |url=http://worldcat.org/oclc/633760282 |title=Computer structures: readings and examples |date=1981 |publisher=McGraw-Hill |isbn=978-0070043572 |oclc=633760282}}</ref> where a [[central processing unit]] (CPU) was designated as ''C'', a variant was noted by the dot notation, and ''mmp'' stood for ''Multi-Mini-Processor''. {{As of|2024}}, the machine is on display at CMU, in Wean Hall, on the ninth floor.
== Structure ==
Sixteen [[Digital Equipment Corporation]] [[PDP-11]] minicomputers were used as the processing elements, named Compute Modules (CMs) in the system. Each CM had a local memory of 8K and a local set of [[peripheral]] devices. One of the challenges was that a device was only available through its unique connected processor, so the [[input/output]] (I/O) system (designed by Roy Levin) hid the connectivity of the devices and routed the requests to the hosting processor. If a processor went down, the devices connected to its [[Unibus]] became unavailable, which became a problem in overall system reliability. Processor 0 (the ''[[Booting|boot]] processor'') had the disk drives attached.
Each of the Compute Modules shared these communication pathways:
* An Interprocessor bus – used to distribute system-wide clock, interrupt, and process control messaging among the CMs
* A 16x16 [[crossbar switch]] – used to connect the 16 CMs on one side and 16 banks of [[shared memory]] on the other. If all 16 processors were accessing different banks of memory, the memory accesses would all be concurrent. If two or more processors were trying to access the same bank of memory, one of them would be granted access on one cycle and the remainder would be negotiated on subsequent memory cycles.
Since the PDP-11 had a logical [[address space]] of 16-bits, another address translation unit was added to expand the address space to 25 bits for the shared memory space. The [[Unibus]] architecture provided 18 bits of [[physical address]], and the two high-order bits were used to select one of four relocation registers which selected a bank of memory. Properly managing these registers was one of the challenges of programming the [[operating system]] (OS) [[Kernel (operating system)|kernel]].
The original C.mmp design used [[magnetic-core memory]], but during its lifetime, higher performance dynamic [[random-access memory]] (RAM) became available and the system was upgraded.
The original processors were PDP-11/20 processors, but in the final system, only five of these were used; the remaining 11 were PDP-11/40 processors, which were modified by having extra writeable microcode space.{{cn|date=August 2023}} All modifications to these machines were designed and built at CMU.
Most of the 11/20 modifications were custom changes to the [[Wire wrap|wire-wrapped]] [[backplane]], but because the PDP-11/40 was implemented in [[microcode]], a separate ''proc-mod'' board was designed that intercepted certain instructions and implemented the protected operating system requirements. For example, it was necessary, for operating system integrity, that the stack pointer register never be odd. On the 11/20, this was done by clipping the lead to the low-order bit of the stack register. On the 11/40, any access to the stack was intercepted by the proc-mod board and generated an illegal data access [[Trap (computing)|trap]] if the low-order bit was 1.
== Operating system ==
The [[operating system]] (OS) was named [[Hydra (operating system)|Hydra]]. It was [[Capability-based security|capability]]-based, [[Object-oriented programming|object-oriented]], [[Multi-user software|multi-user]], and a [[microkernel]]. System resources were represented as [[Object (computer science)|objects]] and protected through capabilities.
The OS and most [[application software]] was written in the [[programming language]] [[BLISS]]-11, which required [[Cross compiler|cross-compiling]] on a [[PDP-10]]. The OS used very little [[assembly language]].
Among the programming languages available on the system was an [[ALGOL 68]] variant which included extensions supporting [[parallel computing]], to make good use of the C.mmp. The ALGOL [[compiler]] ran native on Hydra OS.
== Reliability ==
Because overall system reliability depended on having all 16 CPUs running, there were serious problems with overall hardware reliability. If the [[mean time between failures]] (MTBF) of one processor was 24 hours, then the overall system reliability was 16/24 hours, or about 40 minutes. Overall, the system usually ran for between two and six hours.<ref>{{Cite web|url=http://www.edwardbosworth.com/My5155_Slides/Chapter13/Multiprocessors_02.htm|title=Loosely Coupled Multiprocessors|website=www.edwardbosworth.com|access-date=2018-09-11}}</ref> Many of these failures were due to timing glitches in the many custom circuits added to the processors. Great effort was expended to improve hardware reliability, and when a processor was noticeably failing, it was partitioned out, and would run diagnostics for several hours. When it had passed a first set of diagnostics, it was partitioned back in as an ''I/O processor'' and would not run application code (but its peripheral devices were now available); it continued to run diagnostics. If it passed these after several more hours, it was reinstated as a full member of the processor set. Similarly, if a block of memory (one page) was detected as faulty, it was removed from the pool of available pages, and until otherwise notified, the OS would ignore this page. Thus, the OS became an early example of a ''[[Fault tolerance|fault-tolerant]]'' system, able to deal with hardware problems which arose, inevitably.
==References==
{{Reflist}}
{{refbegin}}
*{{cite report |last1=Wulf |first1=W. A. |last2=Bell |first2=C. G. |author-link=Gordon Bell |date=1972 |url=http://research.microsoft.com/users/GBell/CGB%20Files/Cmmp%20Multi-Mini-Processor%20ComConference%201972%20c.pdf |title=C.mmp: A multi-mini-processor |publisher=Carnegie Mellon University (CMU)}}
*{{cite report |last1=Bell |first1=C. G. |author1-link=Gordon Bell |last2=Broadley |first2=W. |last3=Wulf |first3=W. A. |last4=Newell |first4=A. |author4-link=Allen Newell |last5=Pierson |first5=C. |date=1971 |url=http://link.cs.cmu.edu/files/1971-08-24-CMMP.pdf |title=C.mmp: The CMU Multiminiprocessor Computer: Requirements and Overview of the Initial Design |publisher=Carnegie Mellon University (CMU)}}
*{{cite book |last1=Wulf |first1=Wm. A. |last2=Harbison |first2=S. P. III |date=2000 |title=Readings in Computer Architecture |chapter=Reflections in a Pool of Processors: An Experience Report on C.mmp/Hydra |chapter-url=https://books.google.com/books?id=I7o8teBhz5wC&q=wulf+harbison+c.mmp&pg=PA554 |pages=561–573 |publisher=Gulf Professional Publishing |isbn=9781558605398}}
*{{cite book |last1=Wulf |first1=Wm. A. |last2=Harbison |first2=Samuel P. III |last3=Levin |first3=Roy |date=1 January 1981 |title=HYDRA/C.mmp: An Experimental Computer System |publisher=McGraw-Hill |isbn=978-0070721203}})
{{refend}}
{{Object-capability security}}
{{Microkernel}}
{{Authority control}}
[[Category:Capability systems]]
[[Category:History of computing]]
[[Category:Parallel computing]]