View source for Chip-scale package

{{Short description|Integrated circuit package that is no or barely larger than the die it contains}}
[[Image:UNIO WLCSP and SOT23 Device on Penny.jpg|thumb|right|Top and bottom of a WL-CSP package sitting on the face of a [[U.S. penny]]. In the top-right, a [[SOT-23|SOT23]] package is shown for comparison.]]
A '''chip scale package''' or '''chip-scale package''' ('''CSP''') is a type of [[integrated circuit]] package.<ref>{{cite web |url=https://www.analog.com/en/technical-articles/flipchip--chipscale-package-tech--applications.html |title=Understanding Flip-Chip and Chip-Scale Package Technologies and Their Applications |work=Application Note 4002 |publisher=Maxim Integrated Products (now Analog Devices) |date=April 18, 2007 |accessdate=February 13, 2023}}</ref>
Originally, CSP was the acronym for ''chip-size packaging.'' Since only a few packages are chip size, the meaning of the acronym was adapted to ''chip-scale packaging''. According to [[IPC (electronics)|IPC]]'s standard J-STD-012, ''Implementation of Flip Chip and Chip Scale Technology'', in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the [[die (integrated circuit)|die]] and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1&nbsp;mm.
The concept was first proposed by Junichi Kasai of [[Fujitsu]] and Gen Murakami of [[Hitachi Cable]] in 1993. The first concept demonstration however came from [[Mitsubishi Electric]].<ref>{{cite book |first1=Karl J. |last1=Puttlitz |first2=Paul A. |last2=Totta |title=Area Array Interconnection Handbook |date=December 6, 2012 |publisher=[[Springer Science+Business Media]] |isbn=978-1-4615-1389-6 |page=702}}</ref>
The die may be mounted on an [[interposer]] upon which pads or balls are formed, like with [[flip chip]] [[ball grid array]] (BGA) packaging, or the pads may be etched or printed directly onto the [[silicon wafer]], resulting in a package very close to the size of the silicon die: such a package is called a [[wafer-level package]] (WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as [[Advanced Semiconductor Engineering]] (ASE).<ref>{{cite web |url=https://www.edn.com/electronics-news/4356671/Wafer-Scale-Emerging |title=Wafer Scale Emerging |first=Brandon |last=Prior |work=[[EDN (magazine)|EDN]] |date=January 22, 2001 |accessdate=March 31, 2016}}</ref><ref>{{cite web |url=http://www.edn.com/electronics-news/4348976/ASE-Ramps-Wafer-Level-CSP-Production |title=ASE Ramps Wafer Level CSP Production |work=EDN |date=October 12, 2001 |accessdate=March 31, 2016}}</ref>
==Types==
Chip scale packages can be classified into the following groups:
# Customized leadframe-based CSP (LFCSP)
# Flexible substrate-based CSP
# Flip-chip CSP (FCCSP)
# Rigid substrate-based CSP
# Wafer-level redistribution CSP (WL-CSP)
==References==
{{Reflist}}
==External links==
{{Commons category|CSP integrated circuit packages}}
*[http://www.jedec.org/standards-documents/dictionary/terms/chip-scale-package Definition] by [[JEDEC]]
*[https://web.archive.org/web/20080222135909/http://extra.ivf.se/ngl/D-CSP/ChapterD.htm The Nordic Electronics Packaging Guideline, Chapter D: Chip Scale Packaging]
{{Semiconductor packages}}
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[[Category:Chip carriers| ]]