View source for Die shrink

{{Short description|Process of scaling down the size of semiconductor devices}}
{{Refimprove|date=February 2017}}
{{Semiconductor manufacturing processes}}
The term '''die shrink''' (sometimes '''optical shrink''' or '''process shrink''') refers to the [[List of semiconductor scale examples|scaling]] of [[metal–oxide–semiconductor]] (MOS) devices.  The act of shrinking a [[Die (integrated circuit)|die]] creates a somewhat identical circuit using a more advanced [[fabrication process]], usually involving an advance of [[lithographic]] [[semiconductor node|nodes]]. This reduces overall costs for a chip company, as the absence of major architectural changes to the processor lowers research and development costs while at the same time allowing more processor dies to be manufactured on the same piece of [[silicon wafer]], resulting in less cost per product sold.
Die shrinks are the key to lower prices and higher performance at [[Semiconductor company|semiconductor companies]] such as [[Samsung Electronics|Samsung]], [[Intel]], [[TSMC]], and [[SK Hynix]], and [[fabless]] manufacturers such as [[Advanced Micro Devices|AMD]] (including the former [[ATI Technologies|ATI]]), [[Nvidia|NVIDIA]] and [[MediaTek]].
==Details==
{{See also|Transistor count}}
Examples in the 2000s include the downscaling of the [[PlayStation 2]]'s [[Emotion Engine]] processor from [[Sony]] and [[Toshiba]] (from [[180 nm]] [[CMOS]] in 2000 to [[90 nm]] CMOS in 2003),<ref name="sony2003">{{cite news |title=EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP |url=https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |access-date=26 June 2019 |publisher=[[Sony]] |date=April 21, 2003}}</ref> the codenamed [[Pentium 4#Cedar Mill|Cedar Mill]] [[Pentium 4]] processors (from 90&nbsp;nm CMOS to [[65 nm]] CMOS) and [[Penryn (microarchitecture)|Penryn Core 2]] processors (from 65&nbsp;nm CMOS to [[45 nm]] CMOS), the codenamed [[Athlon 64 X2#Brisbane (65 nm SOI)|Brisbane]] [[Athlon 64 X2]] processors (from [[90 nm]] [[Silicon on insulator|SOI]] to [[65 nm]] [[Silicon on insulator|SOI]]), various generations of [[Graphics processing unit|GPU]]s from both ATI and NVIDIA, and various generations of [[Random-access memory|RAM]] and [[flash memory]] chips from Samsung, Toshiba and SK Hynix. In January 2010, Intel released [[Clarkdale (microprocessor)|Clarkdale]] [[List of Intel Core i5 microprocessors|Core i5]] and [[Intel Core#Core i7|Core i7]] processors fabricated with a [[32 nm]] process, down from a previous [[45 nm]] process used in older iterations of the [[Nehalem (microarchitecture)|Nehalem]] [[Central processing unit|processor]] [[microarchitecture]]. Intel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through its [[Tick-Tock model]]. In this [[business model]], every new [[microarchitecture]] (tock) is followed by a die shrink (tick) to improve performance with the same microarchitecture.<ref name="anandtech-pao">{{cite web|title=Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'|url=http://www.anandtech.com/show/10183/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization|website=Anandtech|access-date=23 March 2016}}</ref>
Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in [[semiconductor devices]] while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased [[clock rate]] headroom, and lower prices.<ref name="anandtech-pao" /> Since the cost to fabricate a 200-mm or 300-mm silicon wafer is proportional to the number of fabrication steps and not proportional to the number of chips on the wafer, die shrinks cram more chips onto each wafer, resulting in lowered manufacturing costs per chip.
==Half-shrink==
In CPU fabrications, a die shrink always involves an advance to a [[Microlithography|lithographic]] node as defined by [[International Technology Roadmap for Semiconductors|ITRS]] (see list). For GPU and [[System on a chip|SoC]] manufacturing, the die shrink often involves shrinking the die on a node not defined by the ITRS, for instance, the 150&nbsp;nm, 110&nbsp;nm, 80&nbsp;nm, 55&nbsp;nm, 40&nbsp;nm and more currently 8&nbsp;nm nodes, sometimes referred to as "half-nodes". This is a stopgap between two ITRS-defined [[lithography|lithographic]] nodes (thus called a "half-node shrink") before further shrink to the lower ITRS-defined nodes occurs, which helps save additional R&D cost. The choice to perform die shrinks to either full nodes or half-nodes rests with the foundry and not the integrated circuit designer.
{| class="wikitable"
|+ Half-shrink
! Main ITRS node
! Stopgap half-node
|-
|[[250 nanometer|250&nbsp;nm]] || 220&nbsp;nm
|-
|[[180&nbsp;nm]] || 150&nbsp;nm
|-
|[[130&nbsp;nm]] || 110&nbsp;nm
|-
|[[90&nbsp;nm]] || 80&nbsp;nm
|-
|[[65&nbsp;nm]] || 55&nbsp;nm
|-
|[[45&nbsp;nm]] || 40&nbsp;nm
|-
|[[32&nbsp;nm]] || 28&nbsp;nm
|-
|[[22&nbsp;nm]] || 20&nbsp;nm
|-
|[[14&nbsp;nm]] || 12&nbsp;nm<ref>{{Cite web | url = http://www.fool.com/investing/2017/01/18/taiwan-semiconductor-mfg-co-ltd-confirms-12nm-tech.aspx | title = Taiwan Semiconductor Mfg. Co. Ltd. Confirms "12nm" Chip Technology Plans |publisher=The Motley Fool |access-date=January 18, 2017}}</ref>
|-
|[[10 nm process|10&nbsp;nm]] || 8&nbsp;nm
|-
|[[7&nbsp;nm]] || 6&nbsp;nm
|-
|[[5&nbsp;nm]] || 4&nbsp;nm
|-
|[[3&nbsp;nm]] || {{n/a}}
|}
==See also==
{{Portal|Electronics}}
* [[Integrated circuit]]
* [[Semiconductor device fabrication]]
* [[Photolithography]]
* [[Moore's law]]
* [[Transistor count]]
==References==
{{Reflist}}
==External links==
* [http://www.onsemi.com/PowerSolutions/content.do?id=16649 0.11 μm Standard Cell ASIC]
* [http://www.eetimes.com/electronics-products/fpga-pld-products/4111039/ON-Semi-offers-110-nm-ASIC-platform EETimes: ON Semi offers 110-nm ASIC platform]
* [https://web.archive.org/web/20111031070456/http://www2.renesas.com/process/en/55nmprocess.html Renesas 55 nm process features]
* [https://web.archive.org/web/20110823041058/http://new.eetimes.com/electronics-news/4213880/RDA-SMIC-make-mixed-signal-IC RDA, SMIC make 55-nm mixed-signal IC]
* [https://web.archive.org/web/20131208074221/http://www.globalfoundries.com/technology/40nm.aspx Globalfoundries 40nm]
* [http://www.umc.com/english/process/f.asp UMC 45/40nm]
* [http://www.eetimes.com/electronics-news/4214792/SiliconBlue-tips-FPGA-move-to-40-nm SiliconBlue tips FPGA move to 40-nm]
* [https://web.archive.org/web/20121107093712/http://globalfoundries.com/technology/28nm.aspx Globalfoundries 28nm, Leading-Edge Technologies]
* [http://www.techpowerup.com/139778/TSMC-Reiterates-28-nm-Readiness-by-Q4-2011.html TSMC Reiterates 28 nm Readiness by Q4 2011]
* [http://www.eetimes.com/electronics-news/4215986/Design-starts-triple-for-TSMC-at-28-nm Design starts triple for TSMC at 28-nm]
[[Category:Integrated circuits]]
[[Category:Semiconductors]]