View source for Epyc

{{Short description|AMD brand for server microprocessors}}
{{confuse|Epic (disambiguation){{!}}Epic}}
{{Use mdy dates|date=January 2024}}
{{Infobox CPU
| name    = Epyc
| image   = [[File:AMD Epyc wordmark.svg|frameless|class=skin-invert]]
| caption =
| produced-start = {{Start date and age|2017|June|20}}
| produced-end =
| slowest = 2.7
| fastest = 5.0
| size-from  = [[14 nm process|14 nm]]
| size-to    = [[3 nm process|3 nm]]
| soldby     = [[AMD]]
| designfirm = [[AMD]]
| manuf1 = [[GlobalFoundries]] ([[14 nm process|14&nbsp;nm]] and [[14 nm process|12&nbsp;nm]])
| manuf2 = [[TSMC]] (7&nbsp;nm and beyond)
| core1  = Naples
| core2  = Rome
| core3  = Milan
| core4  = Genoa
| core5  = Bergamo
| core6  = Siena
| core7  = Raphael
| core8  = Turin
| sock1  = [[Socket AM5|AM5]]<br/>[[Socket SP3|SP3]]<br/>[[Socket SP5|SP5]]<br/>[[Socket SP6|SP6]]
| pack1       =
| arch        = [[AMD64]] (x86-64)
| extensions  = [[MMX (instruction set)|MMX(+)]], [[Streaming SIMD Extensions|SSE1]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4a]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[AVX2]], [[AVX-512]] (with Zen&nbsp;4 and later), [[FMA3 instruction set|FMA3]], [[CVT16 instruction set|CVT16/F16C]], [[Bit Manipulation Instruction Sets#ABM|ABM]], [[Bit Manipulation Instruction Sets#BMI1|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Intel SHA extensions|SHA]], [[Secure Memory Encryption|SME]], [[AMD-V]], [[AMD-Vi]]
| microarch   = {{ubl|'''[[Zen microarchitecture]]:'''|[[Zen (first generation)|Zen]]|[[Zen&nbsp;2]]|[[Zen&nbsp;3]]||[[Zen&nbsp;4]]|[[Zen&nbsp;4c]]|[[Zen&nbsp;5]]|[[Zen&nbsp;5c]]}}
| numcores    = up to 192 cores/384 threads per socket
| memory      = up to 12 memory channels at 6400&nbsp;MT/s
| predecessor = [[Opteron]]
| successor   =
}}
'''Epyc''' (stylized as EPYC) is a brand of [[multi-core]] [[x86-64]] [[microprocessor]]s designed and sold by [[AMD]], based on the company's [[Zen (microarchitecture)|Zen microarchitecture]]. Introduced in June 2017, they are specifically targeted for the [[server (computing)|server]] and [[embedded system]] markets.<ref>{{Cite web |last=Cutress |first=Ian |date=May 30, 2017 |title=Computex 2017: AMD Press Event Live Blog |url=https://www.anandtech.com/show/11476/computex-2017-amd-press-event-live-blog-starts-10pm-et |website=AnandTech |language=en-US |access-date=November 7, 2022}}</ref>
Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more [[PCI Express]] lanes, support for larger amounts of RAM, and larger [[cache memory]]. They also support multi-chip and dual-socket system configurations by using the [[HyperTransport#Infinity Fabric|Infinity Fabric]] interconnect.
== History ==
In March 2017, AMD announced plans to re-enter the server market with a platform based on the [[Zen (microarchitecture)|Zen microarchitecture]], codenamed Naples, and officially revealed it under the brand name Epyc in May.<ref>{{cite news |last1=Kampman |first1=Jeff |date=May 16, 2017 |title=AMD's Naples datacenter CPUs will make an Epyc splash |url=https://techreport.com/news/31916/amd-naples-datacenter-cpus-will-make-an-epyc-splash |website=Tech Report |access-date=May 16, 2017}}</ref> That June AMD officially launched Epyc 7001 series processors, offering up to 32 cores per socket, and enabling performance that allowed Epyc to be competitive with the competing [[Xeon|Intel Xeon Scalable]] product line.<ref>{{cite news |last1=Cutress |first1=Ian |date=June 20, 2017 |title=AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis |url=http://www.anandtech.com/show/11551/amds-future-in-servers-new-7000-series-cpus-launched-and-epyc-analysis |publisher=AnandTech |language=en-US |access-date=July 12, 2017}}</ref> In August 2019, the Epyc 7002 "Rome" series processors, based on the [[Zen 2 |Zen&nbsp;2 microarchitecture]], launched, doubling the core count per socket to 64, and increasing per-core performance dramatically over the last generation architecture.
In March 2021, AMD launched the Epyc 7003 "Milan" series, based on the [[Zen 3 |Zen&nbsp;3 microarchitecture]].<ref>{{Cite web |last=Alcorn |first=Paul |date=March 15, 2021 |title=Watch AMD's Epyc 7003 Milan Launch Here |url=https://www.tomshardware.com/news/amd-epyc-7003-series-milan-launch-watch-here |website=Tom's Hardware |language=en-US |access-date=April 5, 2022}}</ref> Epyc Milan brought the same 64 cores as Epyc Rome, but with much higher per-core performance, with the Epyc 7763 beating the Epyc 7702 by up to 22 percent despite having the same number of cores and threads.<ref>{{Cite web |title=AMD EPYC 7763 vs AMD EPYC 7702 [cpubenchmark.net] by PassMark Software |url=https://www.cpubenchmark.net/compare/AMD-EPYC-7763-vs-AMD-EPYC-7702/4207vs3719 |website=CPU Benchmark |access-date=April 5, 2022}}</ref> A refresh of the Epyc 7003 "Milan" series with 3D V-Cache, named Milan-X, launched on March 21, 2022, using the same cores as  Milan, but with an additional 512&nbsp;MB of cache stacked onto the compute dies, bringing the total amount of cache per CPU to 768&nbsp;MB.<ref name=":0" />
In September 2021, [[Oak Ridge National Laboratory]] partnered with AMD and [[Cray|HPE Cray]] to build [[Frontier (supercomputer)|Frontier]], a supercomputer with 9,472 Epyc 7453 CPUs and 37,888 [[AMD Instinct|Instinct]] MI250X GPUs, becoming operational by May 2022. As of November 2023, it is the most powerful supercomputer in the world according to the [[TOP500]], with a peak performance of over 1.6 [[FLOPS|exaFLOPS]].
In November 2021, AMD detailed the upcoming generations of Epyc, and unveiled the new LGA-6096 [[Socket SP5|SP5]] socket that would support the new generations of Epyc chips. Codenamed Genoa, these CPUs are based on the [[Zen 4|Zen&nbsp;4 microarchitecture]] and built on [[TSMC]]'s [[5 nm process|N5]] node, supporting up to 96 cores and 192 threads per socket, alongside 12 channels of [[DDR5 SDRAM|DDR5]]<ref name=":1">{{Cite web |last=Cutress |first=Ian |date=November 8, 2021 |title=AMD Gives Details on EPYC Zen4: Genoa and Bergamo, up to 96 and 128 Cores |url=https://www.anandtech.com/show/17055/amd-gives-details-on-epyc-zen4-genoa-and-bergamo-up-to-96-and-128-cores |publisher=AnandTech |language=en-US |access-date=April 5, 2022}}</ref> and 128 [[PCI Express#PCI Express 5.0|PCIe 5.0]] lanes. Genoa also became the first x86 server CPU to support [[Compute Express Link]] 1.1,<ref>{{Cite web |last=Mujtaba |first=Hassan |date=February 28, 2021 |title=AMD EPYC Genoa CPU Platform Detailed - Up To 96 Zen 4 Cores, 192 Threads, 12-Channel DDR5-5200, 128 PCIe Gen 5 Lanes, SP5 'LGA 6096' Socket |url=https://wccftech.com/amd-epyc-genoa-cpu-platform-detailed-up-to-96-zen-4-cores-12-channel-ddr5-5200-sp5-lga-6096-socket/ |website=Wccftech |language=en-US |access-date=April 5, 2022}}</ref> or CXL, allowing for further expansion of memory and other devices with a high bandwidth interface built on PCIe 5.0. AMD also shared information regarding the sister chip of Genoa, codenamed Bergamo. Bergamo is based on a modified version of Zen&nbsp;4 named Zen&nbsp;4c, designed to allow for much higher core counts and efficiency at the cost of lower single-core performance, targeting [[Cloud computing|cloud providers]] and workloads, compared to traditional [[High-performance computing|high performance computing]] workloads.<ref>{{Cite web |last=servethehome |date=November 8, 2021 |title=AMD Bergamo to hit 128 Cores and Genoa at 96 Cores |url=https://www.servethehome.com/amd-bergamo-to-hit-128-cores-and-genoa-at-96-cores/ |website=ServeTheHome |language=en-US |access-date=April 5, 2022}}</ref> It is compatible with Socket SP5, and supports up to 128 cores and 256 threads per socket.<ref>{{Cite web |last=Mujtaba |first=Hassan |date=January 10, 2022 |title=Another AMD EPYC Genoa 'Zen 4' CPU Leaks Out, This Time A 16 Core Chip With 2 Active CCDs |url=https://wccftech.com/another-amd-epyc-genoa-zen-4-cpu-leaks-out-this-time-a-16-core-chip-with-2-active-ccds/ |website=Wccftech |language=en-US |access-date=April 5, 2022}}</ref>
In November 2022, AMD launched their 4th generation Epyc "Genoa" series of CPUs. Some tech reviewers and customers had already received hardware for testing and benchmarking, and third party benchmarks of Genoa parts were immediately available. The flagship part, the 96 core Epyc 9654, set records for multi-core performance, and showed up to 4× performance compared to Intel's flagship part, the Xeon Platinum 8380. High memory bandwidth and extensive PCIe connectivity removed many bottlenecks, allowing all 96 cores to be utilized in workloads where previous generation Milan chips would have been I/O-bound.
In June 2023, AMD began shipping the 3D V-Cache enabled Genoa-X lineup, a variant of Genoa that uses the same 3D die stacking technology as Milan-X to enable up to 1152&nbsp;MB of L3 cache, a 50% increase over Milan-X, which had a maximum of 768&nbsp;MB of L3 cache.<ref>{{Cite web |last=Smith |first=Ryan |title=AMD: EPYC "Genoa-X" CPUs With 1.1GB of L3 Cache Now Available |url=https://www.anandtech.com/show/18914/amd-epyc-genoax-cpus-with-11gb-of-l3-cache-shipping-now |access-date=September 26, 2023 |publisher=www.anandtech.com}}</ref> On the same day, AMD also announced the release of their cloud optimized Zen&nbsp;4c SKUs, codenamed Bergamo, offering up to 128 cores per socket, utilizing a modified version of the Zen&nbsp;4 core that was optimized for power efficiency and to reduce die space. Zen&nbsp;4c cores do not have any instructions removed compared to standard Zen 4 cores; instead, the amount of L3 cache per CCX is reduced from 32&nbsp;MB to 16&nbsp;MB, and the frequency of the cores is reduced.<ref>{{Cite web |last=Kennedy |first=Patrick |date=July 19, 2023 |title=AMD EPYC Bergamo is a Fantastically Fresh Take on Cloud Native Compute |url=https://www.servethehome.com/amd-epyc-bergamo-epyc-9754-cloud-native-sp5/ |access-date=September 27, 2023 |publisher=ServeTheHome |language=en-US}}</ref> Bergamo is socket compatible with Genoa, using the same SP5 socket and supporting the same CXL, PCIe, and DDR5 capacity as Genoa.<ref>{{Cite web |last=Kennedy |first=Patrick |date=July 19, 2023 |title=AMD EPYC Bergamo is a Fantastically Fresh Take on Cloud Native Compute |url=https://www.servethehome.com/amd-epyc-bergamo-epyc-9754-cloud-native-sp5/ |access-date=September 26, 2023 |website=ServeTheHome |language=en-US}}</ref>
In September 2023, AMD launched their low power and embedded 8004 series of CPUs, codenamed Siena. Siena utilizes a new socket, called SP6, which has a smaller footprint and pin count than the SP5 socket of its contemporary Genoa processors. Siena utilizes the same Zen&nbsp;4c core architecture as Bergamo cloud native processors, allowing up to 64 cores per processor, and the same 6&nbsp;nm I/O die as Bergamo and Genoa, although certain features have been cut down, such as reducing the memory support from 12 channels of DDR5 to only 6, and removing dual socket support.<ref>{{Cite web |last=Kennedy |first=Patrick |date=September 18, 2023 |title=AMD EPYC 8004 Siena Launched for Lower Power EPYC Edge |url=https://www.servethehome.com/amd-epyc-8004-siena-launched-for-lower-power-epyc-edge/ |access-date=September 26, 2023 |website=ServeTheHome |language=en-US}}</ref>
In May 2024, AMD launched the new 4004 series of CPUs, codenamed Raphael. Sharing the same AM5 socket as desktop Ryzen CPUs. In contrast to desktop parts ECC memories are supported. AM5 motherboard manufacturers do not support the 4004 so available options are very limited to devices which are not suitable for desktop use.
In October 10th, 2024, AMD launched the new 9005 series of CPUs, codenamed Turin. Sharing the same SP5 socket as Genoa and Bergamo, Turin came with numerous platform advancements, including the support for up to 6400 MT/s DDR5 memory.<ref>{{Cite web |last=Cozma |first=George |title=AMD's Turin: 5th Gen EPYC Launched |url=https://chipsandcheese.com/p/amds-turin-5th-gen-epyc-launched |access-date=2024-10-14 |website=chipsandcheese.com |language=en}}</ref> Turin also increased the core count and frequency offerings, with Turin offering 128 Zen 5 cores per socket, and Turin Dense offering 192 Zen 5c cores per socket. And with the highest frequency SKU (The EPYC 9575F) having a operating frequency of up to 5 GHz.<ref>{{Cite web |author1=Paul Alcorn |date=2024-10-10 |title=AMD EPYC 'Turin' 9005 Series - we benchmark 192-core Zen 5 chip with 500W TDP |url=https://www.tomshardware.com/pc-components/cpus/amd-launches-epyc-turin-9005-series-our-benchmarks-of-fifth-gen-zen-5-chips-with-up-to-192-cores-500w-tdp |access-date=2024-10-14 |website=Tom's Hardware |language=en}}</ref>
AMD Epyc CPU codenames follow the naming scheme of [[List of cities in Italy|Italian cities]], including [[Milan]], [[Rome]], [[Naples]], [[Genoa]], [[Bergamo]], [[Siena]], [[Turin]] and [[Venice]].
{| class="wikitable nowrap" style="text-align:center;"
|+ AMD Epyc CPU generations<ref>{{cite web |last=Cutress |first=Ian |date=May 27, 2019 |title=AMD Confirms Zen 4 EPYC Codename, and Elaborates on Frontier Supercomputer CPU |url=https://www.anandtech.com/print/14419/amd-confirms-zen-4-epyc-codename-and-elaborates-frontier-cpu |website=AnandTech |language=en-US |access-date=November 7, 2022}}</ref><ref>{{Cite web |last=Bonshor |first=Gavin |date=June 9, 2022 |title=AMD Updated EPYC Roadmap: 5th Gen EPYC "Turin" Announced, Coming by End of 2024 |url=https://www.anandtech.com/show/17437/amd-updated-epyc-roadmap-until-2024-5th-gen-epyc-announced-coming-by-end-of-2024 |website=AnandTech |language=en-US |access-date=November 7, 2022}}</ref><ref>{{Cite web |author=btarunr |date=June 10, 2022 |title=AMD Announces the "Zen 5" Microarchitecture and EPYC "Turin" Processor on 4nm |url=https://www.techpowerup.com/295709/amd-announces-the-zen-5-microarchitecture-and-epyc-turin-processor-on-4nm |website=TechPowerUp |access-date=November 15, 2022}}</ref><ref>{{Cite web |last=Shilov |first=Anthon |date=March 14, 2023 |title=AMD Rolls Out EPYC Embedded 9004 CPUs: Up to 96 Cores |url=https://www.tomshardware.com/news/amd-rolls-out-epyc-embedded-9004-series-cpus |website=Tom's Hardware |language=en-US |access-date=June 15, 2023}}</ref><ref>{{Cite web |last=Shilov |first=Anthon |date=September 18, 2023 |title=AMD Launches EPYC 8004-Series 'Siena' CPUs: Up to 64 Zen 4c Cores |url=https://www.tomshardware.com/news/amd-launches-epyc-8004-series-siena-cpus-up-to-64-zen-4c-cores |website=Tom's Hardware |language=en-US |access-date=September 18, 2023}}</ref>
! Gen
! Year
! Codename
! Product line
! Cores
! Socket
! Memory
|-
! colspan="7" |Server
|-
| 1st
| 2017
| Naples
| 7001 series
| 32 × Zen
| rowspan="4" | [[Socket SP3|SP3]] ([[Land grid array|LGA]])
| rowspan="4" |[[DDR4 SDRAM|DDR4]]
|-
| 2nd
| 2019
| Rome
| 7002 series
| 64 × Zen&nbsp;2
|-
| rowspan="2" | 3rd
| 2021
| Milan
| rowspan="2" | 7003 series
| rowspan="2" | 64 × Zen&nbsp;3
|-
| rowspan="2" | 2022
| Milan-X
|-
| rowspan="5" | 4th
| Genoa
| rowspan="3" | 9004 series
| rowspan="2" | 96 × Zen&nbsp;4
| rowspan="3" | [[Socket SP5|SP5]] (LGA)
| rowspan="7" | [[DDR5 SDRAM|DDR5]]
|-
| rowspan="3" | 2023
| Genoa-X
|-
| Bergamo
| 128 × Zen&nbsp;4c
|-
| Siena
| 8004 series
| 64 × Zen&nbsp;4c
| [[Socket SP6|SP6]] (LGA)
|-
| rowspan="1" | 2024
| Raphael
| 4004 series
| 16 × Zen&nbsp;4
| [[Socket AM5|AM5]] (LGA)
|-
| rowspan=2 | 5th
| rowspan=2 | 2024
| Turin
| rowspan=2 | 9005 series
| 128 × Zen 5
| rowspan=2 | [[Socket SP5|SP5]] (LGA)
|-
| Turin Dense
| 192 × Zen 5c
|-
|6th
|TBA
|Venice
|{{TBA}}
|{{TBA}}
|[[Socket SP7|SP7]] (LGA)
|{{TBA}}
|-
! colspan="7" | Embedded
|-
| 1st
| 2018
| Snowy&nbsp;Owl
| Embedded 3001 series
| 16 × Zen
| [[Socket SP4|SP4]] ([[Ball grid array|BGA]])
| rowspan="3" |DDR4
|-
| 2nd
| 2019
| Naples
| Embedded 7001 series
| 32 × Zen
| rowspan="2" | SP3 (BGA)
|-
| 3rd
| 2021
| Rome
| Embedded 7002 series
| 64 × Zen&nbsp;2
|-
| 4th
| 2023
| Genoa
| Embedded 9004 series
| 96 × Zen&nbsp;4
| SP5 (BGA)
|DDR5
|}
== Design ==
[[File:AMD@7nm(12nmIOD)@Zen2@Rome@EPYC 7702 ES@2S1404E2VJUG5 BB ES DSCx3.jpg|thumb|A [[Decapping|delidded]] second gen Epyc 7702, showing the die configuration]]
Epyc CPUs use a [[multi-chip module]] design to enable higher yields for a CPU than traditional monolithic dies. First generation Epyc CPUs are composed of four 14 nm compute dies, each with up to 8 cores.<ref>{{cite news |last1=Cutress |first1=Ian |date=March 7, 2017 |title=AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2 |url=http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2 |website=AnandTech |language=en-US |access-date=March 7, 2017}}</ref><ref>{{cite news |last1=Morris |first1=John |date=March 13, 2018 |title=Inside GlobalFoundries' long road to the leading edge |url=https://www.zdnet.com/article/inside-globalfoundries-long-road-to-the-leading-edge/ |publisher=ZDNet |language=en-US |access-date=July 17, 2019}}</ref> Cores are symmetrically disabled on dies to create lower binned products with fewer cores but the same I/O and [[memory footprint]]. Second and Third gen Epyc CPUs are composed of eight compute dies built on a 7&nbsp;nm process node, and a large [[input/output]] (I/O) die built on a 14 nm process node.<ref name="anandtech">{{cite news |last1=Smith |first1=Ryan |date=July 26, 2018 |title=AMD "Rome" EPYC CPUs to Be Fabbed By TSMC |url=https://www.anandtech.com/show/13122/amd-rome-epyc-cpus-to-be-fabbed-by-tsmc |work=AnandTech |language=en-US |access-date=June 18, 2019}}</ref> Third gen Milan-X CPUs use advanced through-silicon-vias to stack an additional die on top of each of the 8 compute dies, adding 64&nbsp;MB of L3 cache per die.<ref>{{Cite web |last=Trader |first=Tiffany |date=March 21, 2022 |title=AMD Milan-X CPU with 3D V-Cache Available in Four SKUs, Up to 64-Cores |url=https://www.hpcwire.com/2022/03/21/amd-milan-x-cpu-with-3d-v-cache-available-in-four-skus-up-to-64-cores/ |website=HPC Wire |language=en-US |access-date=May 6, 2022}}</ref>
Epyc CPUs supports both single socket and dual socket operation. In a dual socket configuration, 64 [[PCI Express|PCIe]] lanes from each CPU are allocated to AMD's proprietary [[HyperTransport|Infinity Fabric]] interconnect to allow for full bandwidth between both CPUs.<ref>{{cite news |last1=Johnson |first1=Renee |date=March 7, 2017 |title=AMD's Naples platform prepares to take Zen into the datacenter |url=https://techreport.com/news/31549/amd-naples-platform-prepares-to-take-zen-into-the-datacenter |website=Tech Report |language=en-US |access-date=March 7, 2017}}</ref> Thus, a dual socket configuration has the same number of usable PCIe lanes as a single socket configuration. First generation Epyc CPUs had 128 PCIe 3.0 lanes, while second and third generation had 128 PCIe 4.0 lanes. All current Epyc CPUs are equipped with up to eight channels of DDR4 at varying speeds, though next gen Genoa CPUs are confirmed by AMD to support up to twelve channels of DDR5.<ref name=":1" /><ref name="anand" />
Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding [[Socket AM1]]), Epyc processors are chipset-free&nbsp;- also known as [[system on a chip]]. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some features may require the use of additional controller chips to utilize.
[[File:AMD Epyc 7702 delidded.jpg|thumb|A near-infrared photograph of a delidded second gen Epyc 7702. Each CCD has two CCXs]]
== Reception ==
Initial reception to Epyc was generally positive.<ref name="anand">{{cite news |last1=De Gelas |first1=Johan |last2=Cutress |first2=Ian |date=July 11, 2017 |title=Sizing Up the Servers: Intel's Skylake-SP Xeon vs AMD's EPYC 7000 |url=http://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade |website=AnandTech |language=en-US |access-date=July 11, 2017}}</ref> Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in [[high-performance computing]] and [[big-data]] applications. First generation Epyc fell behind in database tasks compared to [[Intel]]'s [[Xeon]] parts due to higher cache latency.<ref name="anand"/> In 2021 [[Meta Platforms]] selected Epyc chips for its [[metaverse]] data centers.<ref>{{Cite web |last=Sozzi |first=Brian |date=November 8, 2021 |title=Chipmaker AMD just scored a big deal with Meta |url=https://finance.yahoo.com/news/chipmaker-amd-just-scored-a-big-deal-with-meta-160059677.html |publisher=Yahoo! Finance |language=en-US |access-date=November 10, 2022}}</ref>
Epyc Genoa was well received, as it offered improved performance and efficiency compared to previous offerings, though received some criticism for not having 2 [[DIMM]]s per channel configurations validating, with some reviewers calling it an "incomplete platform".<ref>{{Cite web |last=Kennedy |first=Patrick |date=November 22, 2022 |title=Gigabyte has a 48 DIMM 2P AMD EPYC Genoa GPU Server at SC22 |url=https://www.servethehome.com/gigabyte-has-a-48-dimm-2p-amd-epyc-genoa-gpu-server-at-sc22-ampere-altra-nvidia/ |publisher=ServeTheHome |language=en-US |access-date=November 26, 2022}}</ref>
== List of Epyc processors ==
=== Server ===
==== First generation Epyc (Naples) ====
The following table lists the devices using the first generation design.
A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 [[PCI Express|PCIe]] lanes from each processor for the communication between processors.
===== EPYC 7001 series =====
{{AMD Epyc 7000 series}}
[[File:AMD EPYC die.jpg|thumb|A Epyc 7001 die configuration]]
[[File:Amd epyc 7302 socket sp3 IMGP3493 smial wp.jpg|thumb|A second generation Epyc CPU in an SP3 socket]]
==== Second generation Epyc (Rome) ====
[[File:EpycProcessor.jpg|thumb|First generation Epyc processor]]
In November 2018, AMD announced Epyc&nbsp;2 at their Next Horizon event, the second generation of Epyc processors codenamed "Rome" and based on the Zen&nbsp;2 [[microarchitecture]].<ref>{{Cite press release |title=AMD Takes High-Performance Datacenter Computing to the Next Horizon |url=https://www.amd.com/en/press-releases/2018-11-06-amd-takes-high-performance-datacenter-computing-to-the-next-horizon |website=AMD |language=en-US |location=San Francisco, CA |date=November 6, 2018 |access-date=December 6, 2018}}</ref> The processors feature up to eight [[7 nm process|7 nm]]-based "chiplet" processors with a 14&nbsp;nm-based [[Input/output|IO]] chip providing 128 [[PCI Express#PCI Express 4.0|PCIe 4.0]] lanes in the center interconnected via [[HyperTransport#Infinity Fabric|Infinity Fabric]]. The processors support up to 8 channels of [[DDR4 SDRAM|DDR4]] RAM up to 4 [[Terabyte|TB]], and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 [[Simultaneous multithreading|SMT]] threads per socket.<ref>{{cite web |last=Ung |first=Gordon |date=November 7, 2018 |title=What AMD's 64-core 'Rome' server CPU tells us about Ryzen 2 |url=https://www.pcworld.com/article/3319296/components-processors/what-amds-64-core-rome-server-cpu-tells-us-about-ryzen-2.html |website=PCWorld |language=en-US |access-date=November 11, 2018}}</ref> The 7{{nbsp}}nm "Rome" is manufactured by [[TSMC]].<ref name="anandtech"/> It was released on August 7, 2019.<ref>{{Cite press release |title=2nd Gen AMD EPYC Processors Set New Standard for the Modern Datacenter with Record-Breaking Performance and Significant TCO Savings |url=https://www.amd.com/en/press-releases/2019-08-07-2nd-gen-amd-epyc-processors-set-new-standard-for-the-modern-datacenter |website=AMD |language=en-US |location=Santa Clara, CA |date=August 7, 2019|access-date=August 8, 2019}}</ref> It has 39.5 billion transistors.<ref>{{ cite journal |first=Matthew |last=S. Smith |year=2022 |title=Single-Chip Processors Have Reached Their Limits |journal=IEEE Spectrum |volume=59 |issue=7 |page=11 }}</ref>
In April 2020, AMD launched three new SKUs using Epyc’s 7nm Rome platform. The three processors introduced were the eight-core Epyc 7F32, the 16-core 7F52 and the 24-core 7F72, featuring base clocks up to 3.7&nbsp;GHz (up to 3.9&nbsp;GHz with boost) within a TDP range of 180 to 240 watts. The launch was supported by [[Dell EMC]], [[Hewlett Packard Enterprise]], [[Lenovo]], [[Supermicro]], and [[Nutanix]].<ref>{{cite web |last1=Trader |first1=Tiffany |title=AMD Launches Three New High-Frequency Epyc SKUs Aimed at Commercial HPC |url=https://www.hpcwire.com/2020/04/14/amd-targets-commercial-hpc-with-high-frequency-epyc-7f-series-skus/ |website=www.hpcwire.com |date=April 14, 2020}}</ref>
===== EPYC 7002 series =====
{{AMD Epyc 7002 series}}
[[File:Amd epyc 7302 bottom side with carrier IMGP3326 smial wp.jpg|thumb|The bottom side of an Epyc 7302 mounted in a plastic carrier]]
==== Third generation Epyc (Milan) ====
At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the [[Zen 3|Zen&nbsp;3]] microarchitecture.<ref name="alcorn">{{cite news |last=Alcorn |first=Paul |date=October 5, 2019 |title=AMD dishes on Zen 3 and Zen 4 architecture, Milan and Genoa roadmap|url=https://www.tomshardware.com/news/amd-zen-3-zen-4-epyc-rome-milan-genoa-architecture-microarchitecture,40561.html |website=Tom's Hardware |language=en-US |access-date=October 5, 2019}}</ref> Milan chips will use [[Socket SP3]], with up to 64 cores on package, and support eight-channel [[DDR4 SDRAM|DDR4]] [[Random access memory|RAM]] and 128 [[PCI Express#PCI Express 4.0|PCIe 4.0]] lanes.<ref name="alcorn" /> It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen&nbsp;4 microarchitecture and use [[Socket SP5]].<ref name="alcorn" />
Milan CPUs were launched by AMD on March 15, 2021.<ref>{{Cite web |last=Trader |first=Tiffany |date=March 15, 2021 |title=AMD Launches Epyc 'Milan' with 19 SKUs for HPC, Enterprise and Hyperscale|url=https://www.hpcwire.com/2021/03/15/amd-launches-epyc-milan-with-19-skus-for-hpc-enterprise-and-hyperscale/ |website=HPC Wire |language=en-US |access-date=November 10, 2022}}</ref>
Milan-X CPUs were launched March 21, 2022.<ref name=":0">{{Cite web |title=AMD EPYC 7003 "Milan-X" launches March 21st, specs and pricing leaked |url=https://videocardz.com/newz/amd-epyc-7003-milan-x-launches-march-21st-specs-and-pricing-leaked |website=VideoCardz |language=en-US |date=March 20, 2022 |access-date=March 25, 2022}}</ref> They use 3D V-Cache technology to increase the maximum L3 cache per socket capacity from 256&nbsp;MB to 768&nbsp;MB.<ref>{{cite web |last=Sandhu |first=Tarinder |date=March 21, 2022 |title=A deeper look into AMD Epyc 7003 Milan-X featuring 3D V-Cache |url=https://www.club386.com/amd-unleashes-epyc-7003-series-with-3d-v-cache/ |website=Club386 |language=en-US |access-date=November 10, 2022}}</ref><ref>{{cite web |last=Bonshor |first=Gavin |date=March 21, 2022 |title=AMD Releases Milan-X CPUs With 3D V-Cache: EPYC 7003 Up to 64 Cores and 768 MB L3 Cache |url=https://www.anandtech.com/show/17323/amd-releases-milan-x-cpus-with-3d-vcache-epyc-7003 |website=AnandTech |language=en-US |access-date=November 10, 2022}}</ref><ref>{{Cite web |title=AMDs Exascale-Hammer: Epyc 3 mit 804 MByte Cache, Instinct MI200 mit 47,9 TFlops |url=https://www.heise.de/news/AMDs-Exascale-Hammer-Epyc-3-mit-804-MByte-Cache-Instinct-MI200-mit-47-9-TFlops-6260184.html |website=c't Magazin |language=de |date=November 8, 2021 |access-date=November 10, 2022}}</ref>
===== EPYC 7003 series =====
{{AMD Epyc 7003 series}}
==== Fourth generation Epyc (Genoa, Bergamo and Siena) ====
On November 10, 2022, AMD launched the fourth generation of Epyc server and data center processors based on the Zen&nbsp;4 microarchitecture, codenamed Genoa.<ref>{{cite web |last1=Mujtaba |first1=Hassan |date=November 10, 2022 |title=AMD 4th Gen EPYC 9004 "Genoa Zen 4" CPUs Launched: Up To 96 Cores, 192 Threads, 384 MB L3 Cache & Crushing All Other Server Chips |url=https://wccftech.com/amd-4th-gen-epyc-genoa-zen-4-cpus-official-launch-96-cores-192-threads-worlds-fastest-server-chips/ |website=Wccftech |language=en-US |access-date=November 11, 2022}}</ref> At their launch event, AMD announced that [[Microsoft]] and [[Google]] would be some of Genoa's customers.<ref>{{cite web |last1=Lee |first1=Jane Lanhee |last2=Mehta |first2=Cahvi |date=November 10, 2022 |title=AMD launches data center CPU 'Genoa', taps Google, Microsoft as customers |url=https://www.reuters.com/technology/amd-launches-data-center-cpu-genoa-taps-google-microsoft-customers-2022-11-10/ |website=Reuters |language=en-US |access-date=November 11, 2022}}</ref> Genoa features between 16 and 96 cores with support for [[PCI Express#PCI Express 5.0|PCIe 5.0]] and [[DDR5 SDRAM|DDR5]]. There was also an emphasis by AMD on Genoa's energy efficiency, which according to AMD CEO [[Lisa Su]], means "lower total cost of ownership" for enterprise and cloud datacenter clients.<ref>{{cite web |last1=Burt |first1=Jeffrey |date=November 10, 2022 |title=The Acute Role Reversal for AMD and Intel in Datacenter Compute |url=https://www.nextplatform.com/2022/11/10/the-acute-role-reversal-for-amd-and-intel-in-datacenter-compute/ |website=The Next Platform |language=en-US |access-date=November 11, 2022}}</ref> Genoa uses AMD's new [[Socket SP5|SP5]] (LGA 6096) socket.<ref>{{cite web |last1=Alcorn |first1=Paul |date=November 10, 2022 |title=AMD 4th-Gen EPYC Genoa 9654, 9554, and 9374F Review: 96 Cores, Zen 4 and 5nm Disrupt the Data Center |url=https://www.tomshardware.com/reviews/amd-4th-gen-epyc-genoa-9654-9554-and-9374f-review-96-cores-zen-4-and-5nm-disrupt-the-data-center |website=Tom's Hardware |language=en-US |access-date=November 11, 2022}}</ref>
On June 13, 2023, AMD introduced Genoa-X with 3D V-Cache technology for technical computing performance and Bergamo (9734, 9754 and 9754S) for cloud native computing.<ref>{{cite web |title=AMD Expands 4th Gen EPYC CPU Portfolio with Leadership Processors for Cloud Native and Technical Computing Workloads |url=https://www.amd.com/en/newsroom/press-releases/2023-6-13-amd-expands-4th-gen-epyc-cpu-portfolio-with-leader.html |website=amd.com |access-date=June 14, 2023 |location=Santa Clara, California |date=June 13, 2023}}</ref>
On September 18, 2023, AMD introduced the low power Siena lineup of processors, based on the Zen&nbsp;4c microarchitecture. Siena supports up to 64 cores on the new SP6 socket, which is currently only used by Siena processors. Siena uses the same I/O die as Bergamo, however certain features, such as dual socket support, are removed, and other features are reduced, such as the change from 12 channel memory support to 6 channel memory support.<ref>{{cite web |title=AMD Completes 4th Gen EPYC Family with the AMD EPYC 8004 Processors, Purpose Built for Cloud Services, Intelligent Edge and Telco |url=https://www.amd.com/en/newsroom/press-releases/2023-9-18-amd-completes-4th-gen-epyc-family-with-the-amd-epy.html |website=amd.com |access-date=September 18, 2023 |location=Santa Clara, California |date=June 13, 2023}}</ref>
In May 2024, AMD launched the Raphael lineup of processors, based on the Zen4 microarchitecture. Raphael support up to 16 cores on the AM5 socket.
{{AMD Epyc 9004 series}}
==== Fifth generation Epyc (Turin and Turin Dense) ====
The fifth generation of Epyc processors were showcased by AMD at Computex 2024 on June 3. Named the Epyc 9005 series, it will come in two variants:<ref>{{cite web |last1=Alcorn |first1=Paul |title=AMD announces 3nm EPYC Turin with 192 cores and 384 threads — 5.4X faster than Intel Xeon in AI work, launches second half of 2024 |url=https://www.tomshardware.com/pc-components/cpus/amd-announces-3nm-epyc-turin-launching-with-192-cores-and-384-threads-in-second-half-of-2024-54x-faster-than-intel-xeon-in-ai-workload |website=Tom's Hardware |access-date=17 June 2024 |language=en |date=3 June 2024}}</ref>
* [[Zen 5]] based, up to 128 cores and 256 threads, built on [[TSMC]] [[5 nm process|N4X]] process
* [[Zen 5c]] based, up to 192 cores and 384 threads, built on [[TSMC]] [[3 nm process|N3E]] process
Both variants are officially referred to under the ''Turin'' codename by AMD, although the nickname of "Turin Dense" has also been used to refer to the Zen 5c based CPUs.<ref>{{cite web |title=AMD EPYC Turin CPUs have been pictured, up to 128 Zen5 or 192 Zen5c cores |url=https://videocardz.com/newz/amd-epyc-turin-cpus-have-been-pictured-up-to-128-zen5-or-192-zen5c-cores |website=VideoCardz.com |access-date=17 June 2024 |date=17 December 2023}}</ref>
Turin Dense support the x2AVIC CPU feature
Both of these processor series will be socket-compatible with the SP5 socket used by Genoa and Bergamo. Epyc 9005 series were launched in 10 October 2024 at AMD's Advancing AI event 2024.<ref>{{cite web |title=AMD Launches 5th Gen AMD EPYC CPUs, Maintaining Leadership Performance and Features for the Modern Data Center |url=https://ir.amd.com/news-events/press-releases/detail/1219/amd-launches-5th-gen-amd-epyc-cpus-maintaining-leadership |website=ir.amd.com |access-date=10 October 2024 |date=10 October 2024}}</ref>
{{AMD Epyc 9005 series}}
=== Embedded ===
==== First generation Epyc (Snowy Owl) ====
In February 2018, AMD also announced the Epyc 3000 series of embedded Zen CPUs.<ref name="tomshardware">{{cite news |last1=Alcorn |first1=Paul |date=February 21, 2018 |title=AMD Launches Ryzen Embedded V1000, EPYC Embedded 3000 Processors |url=http://www.tomshardware.com/news/amd-epyc-ryzen-embedded-v1000-3000,36556.html |website=Tom's Hardware |language=en-US |access-date=April 5, 2018}}</ref>
{{AMD Epyc 3000 series}}
== Chinese variants ==
{{Main article|Hygon Information Technology}}
A variant created for the Chinese server market by [[Hygon Information Technology]] is the ''Hygon Dhyana'' [[system on a chip]].<ref name="2018-toms-hardware">{{cite news |last1=Alcorn |first1=Paul |date=July 6, 2018 |title=China Finds Zen: Begins Production Of x86 Processors Based On AMD's IP |url=https://www.tomshardware.com/news/china-zen-x86-processor-dryhana,37417.html |website=Tom's Hardware |language=en-US |access-date=July 9, 2018}}</ref><ref name="2018-phoronix">{{cite news |last1=Larabel |first1=Michael |date=June 9, 2018 |title=Hygon Dhyana: Chinese x86 Server CPUs Based On AMD Zen |url=https://www.phoronix.com/scan.php?page=news_item&px=Hygon-Dhyana-AMD-China-CPUs |website=Phoronix |language=en-US |access-date=July 9, 2018}}</ref> It is noted to be a variant of the AMD Epyc, and is so similar that "there is little to no differentiation between the chips".<ref name="2018-toms-hardware" /> It has been noted that there is "less than 200 lines of new kernel code" for [[Linux kernel]] support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market".<ref name="2018-phoronix" /> Later benchmarks showed that certain floating point instructions are performing worse, probably to comply with US [[export restrictions]].<ref name="CutressWilson">{{Cite web |last1=Cutress |first1=Ian |last2=Wilson |first2=Wendell |date=February 27, 2020 |title=Testing a Chinese x86 CPU: A Deep Dive into Zen-based Hygon Dhyana Processors |url=https://www.anandtech.com/show/15493/hygon-dhyana-reviewed-chinese-x86-cpus-amd |website=AnandTech |language=en-US |access-date=September 29, 2020}}</ref> AES and other western [[cryptography]] algorithms are replaced by Chinese variants throughout the design.<ref name="CutressWilson" />
== References ==
{{Reflist}}
{{AMD processors}}
[[Category:AMD x86 microprocessors]]
[[Category:Computer-related introductions in 2017]]