View source for I486

{{Short description|Successor to the Intel 386}}
{{lowercase title}}
{{Use mdy dates|date=October 2018}}
{{Infobox CPU
| name             = i486
| image            = [[File:Intel i486 logo.svg|frameless|upright=0.5]]{{pb}}[[File:80486dx2-large.jpg|frameless|upright=1]]
| caption          = The exposed die of an Intel 486DX2
| manuf1           = Intel, [[IBM]], [[AMD]], [[Texas Instruments]], [[Harris Semiconductor]], [[United Microelectronics Corporation|UMC]], [[STMicroelectronics|SGS Thomson]]
| designfirm       = [[Intel]], with [[Pat Gelsinger]] as chief architect
| produced-start   = April 10, 1989<ref name="Lewnes, Ann 1989, page 2">Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2.</ref>
| produced-end     = September 28, 2007<ref name="i486LastShipment2007"/>
| size-from        = 1 μm
| size-to          = 600 nm
| transistors      = 1.2<ref name="Lewnes, Ann 1989, page 2">Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2.</ref>–1.6 million
| slowest          = 16| slow-unit     =
| fastest          = 100 | fast-unit     = MHz{{efn|AMD versions up to [[Am486|120]] and [[Am5x86|160]] MHz.}}
| fsb-slowest      = 16  | fsb-slow-unit = MHz
| fsb-fastest      = 50  | fsb-fast-unit = MHz
| l1cache       = 8 KB to 16 KB
| arch             = [[x86-16]], [[IA-32]] including [[x87]] (except for "[[i486SX|SX]]" models)
| data-width       = 32 bits<ref name=486ref>{{cite book |author=Intel |title=Embedded Intel486 Processor Hardware Reference Manual (273025-001) |date=July 1997}}</ref>
| address-width    = 32 bits<ref name=486ref/>
| virtual-width    = 32 bits (linear); 46 bits (logical)<ref name=486ref/>
| pack1            = 168-pin [[Pin grid array|PGA]], 196-pin [[PQFP]], 208-pin [[SQFP]]
| predecessor      = [[i386|Intel 386]]
| successor        = [[Pentium (original)|Pentium/i586 (P5)]]
| co-processor     = [[Intel 80487SX]]
| sock1            = PGA168, [[Socket 1]], [[Socket 2|2]], [[Socket 3|3]]
| support status = Unsupported
}}
The [[Intel]] '''486''', officially named '''i486''' and also known as '''80486''', is a [[microprocessor]] introduced in 1989. It is a higher-performance follow-up to the [[i386|Intel 386]]. It represents the fourth generation of [[binary compatible]] CPUs following the [[Intel 8086|8086]] of 1978, the [[Intel 80286]] of 1982, and 1985's [[i386]].
It was the first tightly-[[instruction pipeline|pipelined]]{{efn|Simple instructions spend only a single clock cycle at each pipeline stage.{{efn|name=fn1|}}}} [[x86]] design as well as the first x86 chip to include more than one million transistors. It offered a large on-chip [[Cache (computing)|cache]] and an integrated [[floating-point unit]]. When it was announced, the initial performance was originally published between 15 and 20 [[VAX Unit of Performance|VAX MIPS]], between 37,000 and 49,000 [[Dhrystone|dhrystones per second]], and between 6.1 and 8.2 double-precision [[Whetstone (benchmark)|megawhetstones per second]] for both 25 and 33&nbsp;MHz version.<ref name="Lewnes, Ann 1989, page 2">Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2.</ref>  A typical 50&nbsp;MHz i486 executes 41&nbsp;million [[instructions per second]] Dhrystone MIPS and [[SPECint|SPEC integer]] rating of 27.9.<ref>Chen, Allan, "The 50-MHz Intel486 Microprocessor", Intel Corporation, Microcomputer Solutions, September/October 1991, page 2.</ref> It is approximately twice as fast as the i386 or i286 per [[Clock signal|clock cycle]]. The i486's improved performance is thanks to its five-stage pipeline with all stages bound to a single cycle. The enhanced FPU unit on the chip was significantly faster than the [[i387]] FPU per cycle. The i387 FPU was a separate, optional math coprocessor installed in a motherboard socket alongside the i386.<ref>{{Cite web |last=LotusChain |date=Jan 28, 2024 |title=FPU in CPU |url=https://lotuschain.medium.com/fpu-in-cpu-a67a3bd2f5ea |access-date=2024-09-15 |website=LotusChain Medium}}</ref>
The i486 was succeeded by the [[Pentium (original)|original Pentium]]. Orders were discontinued for the i486 on March 30, 2007 and the last shipments were on September 28, 2007.<ref name="i486LastShipment2007">{{cite web |archive-url=https://web.archive.org/web/20061009060120/http://developer.intel.com/design/pcn/Processors/D0106013.pdf |archive-date=9 October 2006 |url=http://developer.intel.com/design/pcn/Processors/D0106013.pdf |title=Product Change Notification |date=2 May 2006 | page=2 | publisher=Intel | url-status=dead}}</ref>
==History==
The concept of this microprocessor generation was discussed with Pat Gelsinger and [[John Crawford (engineer)|John Crawford]] shortly after the release of [[I386|386 processor]] in 1985.  The team started the computer simulation in early 1987.  They finalized the logic and microcode function during 1988.  The team finalized the database in February 1989 until the [[Tape-out|tape out]] on March 1.  They received the first silicon from the fabrication on March 20.<ref name="Chen, Allan 1989, page 12">Chen, Allan, "Designing A Mainframe on a Chip: Interview with the i486 Microprocessor Design Team", Intel Corporation, Microcomputer Solutions, July/August 1989, page 12.</ref>
The i486 was announced at Spring [[COMDEX|Comdex]] in April 10, 1989.<ref name="Lewnes, Ann 1989, page 2">Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2.</ref> At the announcement, Intel stated that samples would be available in the third quarter and production quantities would ship in the fourth quarter.<ref>486 [[32-bit computing|32-bit]] CPU breaks new ground in chip density and operating performance. (Intel Corp.) (product announcement) EDN, May 11, 1989, Pryce, Dave.</ref> The first i486-based PCs were announced in late 1989.<ref>{{cite news |url = https://www.nytimes.com/1989/10/22/business/the-executive-computer-the-race-to-market-a-486-machine.html?pagewanted=1 |work = The New York Times |title = The Executive Computer; The Race to Market a 486 Machine |first = Peter H. |last = Lewis |date = October 22, 1989 |access-date = May 5, 2010 }}</ref>
In fall of 1991, Intel introduced the 50 MHz i486&nbsp;DX using the three layer [[800&nbsp;nm process]] [[CHMOS|CHMOS-V]] technology. They were available for US$665 in 1,000-unit quantities.<ref>Chen, Allan, "The 50-MHz Intel486 Microprocessor", Intel Corporation, Microcomputer Solutions, September/October 1991, page 2.</ref>
In that season, Intel introduced low-power 25 MHz Intel486&nbsp;DX microprocessor. This one was available for US$471. Also, there were low-power 16, 20, and 25&nbsp;MHz Intel486&nbsp;SX microprocessors. They were available at $235, $266, and $366 for these frequency range respectively. All pricing were in quantities of 1,000 pieces. These low-power microprocessors have power consumption reduced by 50–75% compared to similar regular versions of these CPUs.<ref>Intel Corporation, "New Product Focus: Components: Modified Chips Cuts Portable Power Consumption", Microcomputer Solutions, November/December 1991, page 10.</ref>
The first major update to the i486 design came in March 1992 with the release of the clock-doubled [[Intel DX2|486DX2]] series.<ref name=":0">{{Cite magazine |last=Yates |first=Darren |date=November 2020 |title=Four. Eight. Six. |magazine=[[APC (magazine)|APC]] |language=en |publisher=Future Publishing |issue=486 |pages=52–55 |issn=0725-4415}}</ref> It was the first time that the CPU core clock frequency was separated from the [[system bus]] clock frequency by using a dual clock multiplier, supporting 486DX2 chips at 40 and 50&nbsp;MHz. The faster 66&nbsp;MHz 486DX2-66 was released that August.<ref name=":0" />
The fifth-generation [[Pentium (original)|Pentium]] processor launched in 1993, while Intel continued to produce i486 processors, including the triple-clock-rate [[Intel DX4|486DX4-100]] with a 100&nbsp;MHz clock speed and a L1 cache doubled to 16&nbsp;KB.<ref name=":0" />
Earlier, Intel had decided not to share its 80386 and 80486 technologies with AMD. However, AMD believed that their technology sharing agreement extended to the 80386 as a derivative of the 80286.<ref name=":0" /> AMD reverse-engineered the 386 and produced the 40&nbsp;MHz [[Am386|Am386DX-40]] chip, which was cheaper and had lower power consumption than Intel's best 33&nbsp;MHz version.<ref name=":0" /> Intel attempted to prevent AMD from selling the processor, but AMD won in court, which allowed it to establish itself as a competitor.<ref name=":1">{{Cite web <!--Deny Citation Bot--> |last=Lilly |first=Paul |date=2009-04-14 |title=A Brief History of CPUs: 31 Awesome Years of x86 |url=https://www.pcgamer.com/a-brief-history-of-cpus-31-awesome-years-of-x86/ |access-date=2021-08-07 |website=PC Gamer |language=en}}</ref>
AMD continued to create clones, releasing the first-generation [[Am486]] chip in April 1993 with clock frequencies of 25, 33 and 40&nbsp;MHz. Second-generation Am486DX2 chips with 50, 66 and 80&nbsp;MHz clock frequencies were released the following year.<ref name=":0" /> The Am486 series was completed with a 120&nbsp;MHz DX4 chip in 1995.<ref name=":0" />
AMD's long-running 1987 arbitration lawsuit against Intel was settled in 1995, and AMD gained access to Intel's 80486 microcode.<ref name=":0" /> This led to the creation of two versions of AMD's 486 processor{{snd}} one reverse-engineered from Intel's microcode, while the other used AMD's microcode in a [[clean-room design]] process. However, the settlement also concluded that the 80486 would be AMD's last Intel clone.<ref name=":0" />
Another 486 clone manufacturer was [[Cyrix]], which was a [[Fabless manufacturing|fabless]] co-processor chip maker for 80286/386 systems. The first [[Cyrix Cx486|Cyrix 486]] processors, the 486SLC and 486DLC, were released in 1992 and used the 80386 package.<ref name=":0" /> Both [[Texas Instruments]]-manufactured Cyrix processors were pin-compatible with 386SX/DX systems, which allowed them to become an upgrade option.<ref name=":1" /> However, these chips could not match the Intel 486 processors, having only 1&nbsp;KB of cache memory and no built-in math coprocessor. In 1993, Cyrix released its own Cx486DX and DX2 processors, which were closer in performance to Intel's counterparts. Intel and Cyrix sued each other, with Intel filing for [[patent infringement]], and Cyrix for [[antitrust]] claims. In 1994, Cyrix won the patent infringement case and dropped its antitrust claim.<ref name=":0" />
In 1995, both Cyrix and AMD began looking at a ready market for users wanting to upgrade their processors. Cyrix released a derivative 486 processor called the [[Cyrix 5x86|5x86]], based on the Cyrix M1 core, which was clocked up to 120&nbsp;MHz and was an option for 486 Socket&nbsp;3 motherboards.<ref name=":0" /><ref name=":1" /> AMD released a 133&nbsp;MHz [[Am5x86]] upgrade chip, which was essentially an improved 80486 with double the cache and a quad multiplier that also worked with the original 486DX motherboards.<ref name=":0" /> Am5x86 was the first processor to use AMD's performance rating and was marketed as Am5x86-P75, with claims that it was equivalent to the Pentium&nbsp;75.<ref name=":1" /> [[Kingston Technology]] launched a "TurboChip" 486 system upgrade that used a 133&nbsp;MHz Am5x86.<ref name=":0" />
Intel responded by making a [[Pentium OverDrive]] upgrade chip for 486 motherboards, which was a modified Pentium core that ran up to 83&nbsp;MHz on boards with a 25 or 33&nbsp;MHz front-side bus clock. OverDrive wasn't popular due to speed and price.<ref name=":0" /> New computers equipped with 486 processors in discount warehouses became scarce, and an [[IBM]] spokesperson called it a "dinosaur".<ref name="chauvet-1996">{{cite news |first=Berenice D. |last=Chauvet |work=Sun Sentinel |title=School buys outdated computer model |url=https://www.sun-sentinel.com/news/fl-xpm-1996-07-15-9607140215-story.html |archiveurl=https://web.archive.org/web/20210702154637/https://www.sun-sentinel.com/news/fl-xpm-1996-07-15-9607140215-story.html |archivedate=July 2, 2021 |date=July 15, 1996 |publisher=Tribune Publishing}}</ref> Even after the Pentium series of processors gained a foothold in the market, however, Intel continued to produce 486 cores for industrial embedded applications. Intel discontinued production of i486 processors in late 2007.<ref name="i486LastShipment2007"/><ref name=":0" />
==Improvements==
[[File:80486DX2 arch.svg|300px|thumb|The 486DX2 architecture]]
{| class="infobox" style="font-size:88%;width:34em;"
|-
|+ i486 registers
|-
|
{| style="font-size:88%"
|-
| style="width:10px; text-align:center"| <sup>3</sup><sub>1</sub>
| style="width:120px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:50px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:35px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="8" | '''Main registers''' ''(8/16/32 bits)''
|- style="background:silver;color:black;text-align:left"
| style="text-align:center" colspan="2"| EAX
| style="text-align:center" colspan="2"| AH
| style="text-align:center" colspan="3"| AL
| style="background:white; color:black"| '''A''' register
|- style="background:silver;color:black;text-align:left"
| style="text-align:center" colspan="2"| EBX
| style="text-align:center" colspan="2"| BH
| style="text-align:center" colspan="3"| BL
| style="background:white; color:black"| '''B''' register
|- style="background:silver;color:black;text-align:left"
| style="text-align:center" colspan="2"| ECX
| style="text-align:center" colspan="2"| CH
| style="text-align:center" colspan="3"| CL
| style="background:white; color:black"| '''C''' register
|- style="background:silver;color:black;text-align:left"
| style="text-align:center" colspan="2"| EDX
| style="text-align:center" colspan="2"| DH
| style="text-align:center" colspan="3"| DL
| style="background:white; color:black"| '''D''' register
|-
|colspan="8" | '''Index registers''' ''(16/32 bits)''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| ESI
| style="text-align:center" colspan="5"| SI
| style="background:white; color:black"| '''S'''ource '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| EDI
| style="text-align:center" colspan="5"| DI
| style="background:white; color:black"| '''D'''estination '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| EBP
| style="text-align:center" colspan="5"| BP
| style="background:white; color:black"| '''B'''ase '''P'''ointer
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| ESP
| style="text-align:center" colspan="5"| SP
| style="background:white; color:black"| '''S'''tack '''P'''ointer
|-
|colspan="8" | '''Program counter''' ''(16/32 bits)''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| EIP
| style="text-align:center" colspan="5"| IP
| style="background:white; color:black"| '''I'''nstruction '''P'''ointer
|-
|colspan="8" | '''Segment selectors''' ''(16 bits)''
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| CS
| style="background:white; color:black"| '''C'''ode '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| DS
| style="background:white; color:black"| '''D'''ata '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| ES
| style="background:white; color:black"| '''E'''xtra '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| FS
| style="background:white; color:black"| '''F''' '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| GS
| style="background:white; color:black"| '''G''' '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| SS
| style="background:white; color:black"| '''S'''tack '''S'''egment
|}
|-
|
{| style="font-size:88%"
|-
|colspan="20" | '''Status register'''
|-
| style="width:20px; text-align:center"| &nbsp;
| style="width:10px; text-align:center"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF"| &nbsp;
| style="text-align:center"| [[Virtual 8086 mode|V]]
| style="text-align:center"| R
| style="text-align:center"| 0
| style="text-align:center"| N
| style="text-align:center" colspan="2"| [[IOPL]]
| style="text-align:center"| [[Overflow flag|O]]
| style="text-align:center"| [[Direction flag|D]]
| style="text-align:center"| [[IF (x86 flag)|I]]
| style="text-align:center"| [[Trap flag|T]]
| style="text-align:center"| [[Sign flag|S]]
| style="text-align:center"| [[Zero flag|Z]]
| style="text-align:center"| 0
| style="text-align:center"| [[Adjust flag|A]]
| style="text-align:center"| 0
| style="text-align:center"| [[Parity flag|P]]
| style="text-align:center"| 1
| style="text-align:center"| [[Carry flag|C]]
| style="background:white; color:black" | [[FLAGS register|EFlags]]
|}
|-
|
{| style="font-size:88%"
|-
|colspan="3" | '''Floating-point registers''' ''(80 bits)''
|-
| style="width:10px; text-align:center"| <sup>7</sup><sub>9</sub>
| style="width:245px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- style="background:silver"
| style="text-align:center" colspan="3"| ST0
| style="background:white; color:black" | '''ST'''ack register 0
|- style="background:silver"
| style="text-align:center" colspan="3"| ST1
| style="background:white; color:black" | '''ST'''ack register 1
|- style="background:silver"
| style="text-align:center" colspan="3"| ST2
| style="background:white; color:black" | '''ST'''ack register 2
|- style="background:silver"
| style="text-align:center" colspan="3"| ST3
| style="background:white; color:black" | '''ST'''ack register 3
|- style="background:silver"
| style="text-align:center" colspan="3"| ST4
| style="background:white; color:black" | '''ST'''ack register 4
|- style="background:silver"
| style="text-align:center" colspan="3"| ST5
| style="background:white; color:black" | '''ST'''ack register 5
|- style="background:silver"
| style="text-align:center" colspan="3"| ST6
| style="background:white; color:black" | '''ST'''ack register 6
|- style="background:silver"
| style="text-align:center" colspan="3"| ST7
| style="background:white; color:black" | '''ST'''ack register 7
|}
|}
The [[instruction set]] of the i486 is very similar to the i386, with the addition of a few extra instructions, such as CMPXCHG, a [[compare-and-swap]] [[atomic operation]], and XADD, a [[fetch-and-add]] atomic operation that returned the original value (unlike a standard ADD, which returns flags only).  This generation CPU has brought up to 156 different instructions listing.<ref>House, Dave, "Putting the RISC vs. CISC Debate to Rest", Intel Corporation, Microcomputer Solutions, November/December 1991, page 18</ref>
The i486's performance architecture is a vast improvement over the i386. It has an on-chip unified instruction and data [[CPU cache|cache]], an on-chip [[floating-point unit]] (FPU) and an enhanced [[computer bus|bus]] interface unit.<ref>{{FOLDOC|i486}}</ref> Due to the tight pipelining, sequences of simple instructions (such as <code>ALU reg,reg</code> and <code>ALU reg,im</code>) could sustain single-clock-cycle throughput (one instruction completed every clock). In other words, it was running about 1.8 clocks per instruction.<ref name="Chen, Allan 1989, page 12"/>  These improvements yielded a rough doubling in integer [[Arithmetic logic unit|ALU]] performance over the i386 at the same [[clock rate]]. A 16&nbsp;MHz i486 therefore had performance similar to a 33&nbsp;MHz i386. With the combination both CPU and NPU house in the die would have bus utilization rate of 50% for the 25 MHz Intel486 version.<ref>Intel Corporation, "Coming Attractions: Clock-Doubling Technology", Microcomputer Solutions, January/February 1992, page 6</ref> In other words, with the combination of both CPU and MCP (math coprocessor) provides 40% more performance than with both Intel386 DX and Intel387 DX math coprocessor combined.<ref>Intel Corporation, "A Guide to the Intel Architecture", Microcomputer Solutions, January/February 1992, page 11</ref>  The older design had to reach 50&nbsp;MHz to be comparable with a 25&nbsp;MHz i486 part.{{efn|The pre-DX2 i486 parts did not use a clock multiplier and are therefore comparable to a twice-higher clocked 386/286.}}
===Differences between i386 and i486===
* An 8 [[Kilobyte|KB]] on-chip (level 1) [[Static random access memory|SRAM]] [[CPU cache|cache]] stores the most recently used instructions and data (16&nbsp;KB and/or [[Cache (computing)#Operation|write-back]] on some later models). The [[i386]] had no internal cache but supported a slower off-chip cache (not officially a [[level 2 cache]] because i386 had no internal level 1 cache).
* An enhanced external bus protocol to enable cache coherency and a new burst mode for memory accesses to fill a cache line of 16 bytes within five bus cycles. The 386 needed eight bus cycles to transfer the same amount of data.
* Tightly coupled{{efn|name=fn1|The 386, 286, and even the 8086 all had overlapping fetch, decode, execution (calculation), and write back; however, '''tightly pipelined''' usually means that all stages perform their respective duties within the same length time slot. In contrast '''loosely pipelined''' implies that some kind of buffering is used to decouple the units and allow them to work more independently. Both the original 8086 and the x86-chips of today are "loosely pipelined" in this sense, while the i486 and the original Pentium worked in a "tightly pipelined" manner for typical instructions. This included most "[[Complex instruction set computing|CISC]]" type instructions as well as the simple load/store-free "[[RISC]]-like" ones, although the most complex also used some dedicated [[microcode]] control.}} [[Instruction pipeline|pipelining]] completes a simple instruction like ALU ''reg,reg'' or ALU ''reg,im'' every clock cycle (after a latency of several cycles). The i386 needed two clock cycles.
* Integrated [[floating point unit|FPU]] (disabled or absent in [[Intel 80486SX|SX models]]) with a dedicated [[local bus]]; together with faster algorithms on more extensive hardware than in the i387, this performed floating-point calculations faster than the [[i386]]/[[i387]] combination.
* Improved [[memory management unit|MMU]] performance.
* New instructions: XADD, BSWAP, CMPXCHG, INVD, WBINVD, INVLPG.
Just as in the i386, a flat 4&nbsp;GB memory model could be implemented. All "segment selector" registers could be set to a neutral value in [[protected mode]], or to zero in [[real mode]], and using only the 32-bit "offset registers" (x86-terminology for general CPU registers used as address registers) as a linear 32-bit virtual address bypassing the segmentation logic. Virtual addresses were then normally mapped onto physical addresses by the paging system except when it was disabled (''real'' mode had no ''virtual'' addresses). Just as with the i386, circumventing memory segmentation could substantially improve performance for some [[operating systems]] and applications.
On a typical PC [[motherboard]], either four matched 30-pin (8-bit) [[SIMM]]s or one 72-pin (32-bit) SIMM per bank were required to fit the i486's [[32-bit computing|32-bit]] [[bus (computing)|data bus]]. The [[address bus]] used 30-bits (A31..A2) complemented by four byte-select pins (instead of A0,A1) to allow for any 8/16/32-bit selection. This meant that the limit of directly addressable physical memory was 4&nbsp;[[gigabyte]]s as well (2<sup>30</sup> ''32-bit'' words = 2<sup>32</sup> ''8-bit'' words).
==Models==
Intel offered several suffixes and variants (see table). Variants include:
* ''[[RapidCAD|Intel RapidCAD]]'': a specially packaged Intel 486DX and a dummy [[floating-point unit]] (FPU) designed as pin-compatible replacements for an [[i386]] processor and [[Intel 80387|80387]] FPU.
* ''i486SL-NM'': i486SL based on i486SX.
* ''[[Intel 80487SX|i487SX (P23N)]]'': i486DX with one extra pin sold as an FPU upgrade to [[i486SX]] systems; When the i487SX was installed, it ensured that an i486SX was present on the [[motherboard]] but disabled it, taking over all of its functions.
* ''[[Intel 80486 OverDrive|i486 OverDrive (P23T/P24T)]]'': i486SX, i486SX2, i486DX2 or i486DX4. Marked as upgrade processors, some models had different pinouts or voltage-handling abilities from "standard" chips of the same speed. Fitted to a coprocessor or "OverDrive" socket on the motherboard, they worked the same as the i487SX.
The maximal internal clock frequency (on Intel's versions) ranged from 16 to 100&nbsp;MHz. The 16&nbsp;MHz i486SX model was used by [[Dell Computers]].
One of the few i486 models specified for a 50&nbsp;MHz bus (486DX-50) initially had overheating problems and was moved to the 0.8-[[Micrometre|micrometer]] fabrication process. However, problems continued when the 486DX-50 was installed in local-bus systems due to the high bus speed, making it unpopular with mainstream consumers. Local-bus video was considered a requirement at the time, though it remained popular with users of [[Extended Industry Standard Architecture|EISA]] systems. The 486DX-50 was soon eclipsed by the clock-doubled [[Intel 80486DX2|i486DX2]], which although running the internal CPU logic at twice the external bus speed (50&nbsp;MHz), was nevertheless slower because the external bus ran at only 25&nbsp;MHz. The i486DX2 at 66&nbsp;MHz (with 33&nbsp;MHz external bus) was faster than the 486DX-50, overall.
More powerful i486 iterations such as the OverDrive and [[DX4]] were less popular (the latter available as an OEM part only), as they came out after Intel had released the [[Pentium (original)|next-generation Pentium]] processor family. Certain steppings of the DX4 also officially supported 50&nbsp;MHz bus operation, but it was a seldom-used feature.
:{| class="wikitable"
! || Model || CPU/bus<br />clock speed || [[VCore|Voltage]] || [[L1 cache]]{{efn|1=''WT'' = write-through cache strategy, ''WB'' = write-back cache strategy.}} || Introduced
! width="520px" | Notes
|-
| [[File:Intel i486 DX 25MHz SX328.jpg|80px]][[File:Intel i486 DX-33.jpg|80px]][[File:Intel i486 dx 50mhz 2007 03 27.jpg|80px]] || i486DX (P4) || 20, 25&nbsp;MHz<br />33&nbsp;MHz<br />50&nbsp;MHz || 5 V || 8&nbsp;KB WT || April 1989<br />May 1990<br />June 1991 || The original chip without clock multiplier
|-
| {{Anchor|486SL}}[[File:KL Intel 486SL.jpg|80px]] || i486SL || 20, 25, 33&nbsp;MHz || 5 V or 3.3 V || 8&nbsp;KB WT || November 1992 || Low-power version of the i486DX, reduced VCore, SMM ([[System Management Mode]]), stop clock, and power-saving features — mainly for use in portable computers
|-
| [[File:Intel i486 sx 33mhz 2007 03 27.jpg|80px]] || i486SX (P23) || 16, 20, 25&nbsp;MHz<br />33&nbsp;MHz || 5 V || 8&nbsp;KB WT || September 1991<br />September 1992 || An i486DX with the FPU part disabled; later versions had the FPU removed from the [[Integrated circuit|die]] to reduce area and hence cost.
|-
| [[File:Intel i486 dx2 66mhz 2007 03 27.jpg|80px]] || i486DX2 (P24) || 40/20, 50/25&nbsp;MHz<br />66/33&nbsp;MHz || 5 V || 8&nbsp;KB WT || March 1992<br />August 1992 || The internal processor clock runs at twice the [[clock rate]] of the external bus clock
|-
| || i486DX-S (P4S) || 33&nbsp;MHz; 50&nbsp;MHz || 5 V or 3.3 V || 8&nbsp;KB WT || June 1993 || SL Enhanced 486DX
|-
| [[File:KL Intel i486DX2 PQFP.jpg|80px]] || i486DX2-S (P24S) || 40/20&nbsp;MHz,<br />50/25&nbsp;MHz,<br />(''66/33&nbsp;MHz'') || 5 V or 3.3 V || 8&nbsp;KB WT || June 1993 || SL Enhanced 486DX2
|-
| [[File:KL Intel i486SX PQFP.jpg|80px]] || i486SX-S (P23S)|| 25, 33&nbsp;MHz || 5 V or 3.3 V || 8&nbsp;KB WT || June 1993 || SL Enhanced 486SX
|-
| [[File:KL intel i486SX2.jpg|80px]] || i486SX2 || 50/25, 66/33&nbsp;MHz || 5 V || 8&nbsp;KB WT || March 1994 || i486DX2 with the FPU disabled. Early version used the 800 nm process technology.<ref>Intel Corporation, "Coming Attractions: Clock-Doubling Technology", Microcomputer Solutions, January/February 1992, page 6.</ref>
|-
| [[File:FC80486DX4-75 AK SX883 USA 1995 01 WT.jpg|80px]][[File:Intel i486 DX4 100 MHz SK051.jpeg|80px]]|| IntelDX4 (P24C) || 75/25, 100/33&nbsp;MHz || 3.3 V || 16&nbsp;KB WT || March 1994 || Designed to run at triple clock rate (not quadruple, as often believed; the DX3, which was meant to run at 2.5× the clock speed, was never released). DX4 models that featured write-back cache were identified by an "&EW" laser-etched into their top surface, while the write-through models were identified by "&E".
|-
| [[File:Intel i486 DX2 66 CPU SX955.jpg|80px]]|| i486DX2WB (P24D)|| 50/25&nbsp;MHz,<br />66/33&nbsp;MHz || 5 V || 8&nbsp;KB WB || October 1994 || Enabled write-back cache.
|-
| [[File:Intel i486 dx4 100mhz 2007 03 27.jpg|80px]] || IntelDX4WB || 100/33&nbsp;MHz || 3.3 V || 16&nbsp;KB&nbsp;WB || October 1994 ||
|-
| || i486DX2 (P24LM) || 90/30&nbsp;MHz,<br />100/33&nbsp;MHz || 2.5–2.9 V || 8&nbsp;KB WT || 1994 ||
|-
| [[File:KL Intel i486GX.jpg|80px]]|| i486GX || up to 33&nbsp;MHz || 3.3 V || 8&nbsp;KB WT || || Embedded ultra-low-power CPU with all features of the i486SX and 16-bit external data bus. This CPU is for embedded battery-operated and hand-held applications.
|}
<!-- Should we specify what is meant by the slashes in this table?  Does 66/33&nbsp;MHz mean internal (doubled) clock 66&nbsp;MHz, external clock (oscillator and bus) 33&nbsp;MHz, as I think it does?  Why is i486DX2 (P24LM) listed with 30/90; 33/100 indicated in the reverse order?  Does inclusion of that last processor in this list imply something errant about the comment later that only AMD made the 90/30&nbsp;MHz grade? --Are the data in this table all Intel models, or are all other compatible processors included?  Either a title should be added showing this to be a table of Intel models only, or a "Manufacturer" column should be added, I think. -->
<!-- Was the 80486 the first Intel x86 CPU to be offered by Intel in a "mobile" version, optimized for battery-powered portable computers?  The 386 might have had such an offering. -->
==Other makers of 486-like CPUs==
[[File:KL STMicroelectronics ST486DX2-40.jpg|thumb|150px|STMicroelectronics' ST ST486DX2-40]]
[[File:KL UMC U5SX.jpg|thumb|150px|[[UMC Green CPU]] U5SX]]
[[Image:KL Cyrix 486DRx2.jpg|thumb|right|150px|Cyrix Cx486DRx²]]
Processors compatible with the i486 were produced by companies such as [[IBM]], [[Texas Instruments]], [[AMD]], [[Cyrix]], [[United Microelectronics Corporation|UMC]], and [[STMicroelectronics]] (formerly SGS-Thomson). Some were clones (identical at the microarchitectural level), others were [[clean room design|clean room implementations]] of the Intel instruction set. (IBM's multiple-source requirement was one of the reasons behind its x86 manufacturing since the 80286.)  The i486 was, however, covered by many Intel patents, including from the prior i386.  Intel and IBM had broad cross-licenses of these patents, and AMD was granted rights to the relevant patents in the 1995 settlement of a lawsuit between the companies.<ref>{{cite web|title=AMD-Intel Litigation History|url=https://yannalaw.com/services/trials-litigation/litigation-cottage-industry/amd-intel-litigation/|website=yannalaw.com}}</ref>
AMD produced several clones using a 40&nbsp;MHz bus (486DX-40, 486DX/2-80, and 486DX/4-120) which had no Intel equivalent, as well as a part specified for 90&nbsp;MHz, using a 30&nbsp;MHz external clock, that was sold only to OEMs. The fastest running i486-compatible CPU, the [[Am5x86]], ran at 133&nbsp;MHz and was released by AMD in 1995. 150&nbsp;MHz and 160&nbsp;MHz parts were planned but never officially released.
Cyrix made a variety of i486-compatible processors, positioned at the cost-sensitive desktop and low-power (laptop) markets.  Unlike AMD's 486 clones, the Cyrix processors were the result of clean-room reverse engineering. Cyrix's early offerings included the 486DLC and 486SLC, two hybrid chips that plugged into 386DX or SX sockets respectively, and offered 1&nbsp;KB of cache (versus 8&nbsp;KB for the then-current Intel/AMD parts). Cyrix also made "real" 486 processors, which plugged into the i486's socket and offered 2 or 8&nbsp;KB of cache. Clock-for-clock, the Cyrix-made chips were generally slower than their Intel/AMD equivalents, though later products with 8&nbsp;KB caches were more competitive, albeit late to market.
The [[Motorola 68040]], while not i486 compatible, was often positioned as its equivalent in features and performance. Clock-for-clock basis the [[Motorola 68040]] could significantly outperform the Intel chip.<ref>{{cite web|title=CISC: The Intel 80486 vs. The Motorola MC68040|url=http://textfiles.meulie.net/computers/486vs040.txt|access-date=May 20, 2013|date=July 1992}}</ref><ref>[http://www.bbs.ingedigit.com.ve/TechInfo/68040.Microprocessor.html 68040 Microprocessor] {{webarchive |url=https://web.archive.org/web/20120216013510/http://www.bbs.ingedigit.com.ve/TechInfo/68040.Microprocessor.html |date=February 16, 2012 }}</ref> However, the i486 had the ability to be clocked significantly faster without overheating. [[Motorola 68040]] performance lagged behind the later production i486 systems.{{Citation needed|date=July 2015}}
==Motherboards and buses==
{{unreferenced section|date=March 2021}}
[[File:Byte magazine September 1989 cover.png|thumb|200px|The [[Apricot Computers|first 486 system from the UK]] on the cover of BYTE, September 1989]]
Early i486-based computers were equipped with several [[Industry Standard Architecture|ISA]] slots (using an [[emulated]] [[Industry Standard Architecture|PC/AT-bus]]) and sometimes one or two [[8-bit computing|8-bit]]-only slots (compatible with the PC/XT-bus).{{efn|In general, 8-bit ISA slots in these systems were implemented just by leaving off the shorter "C"/"D" connector of the slot, though the copper traces for a 16-bit slot were still there on the motherboard; the computer could tell no difference between an 8-bit ISA adapter in such a slot and the same adapter in a 16-bit slot, and there were still enough 8-bit adapters in circulation that vendors figured they could save money on a few connectors this way. Also, leaving off the 16-bit extension to the ISA connector allowed use of some early 8-bit ISA cards that otherwise could not be used due to the PCB "skirt" hanging down into that 16-bit extension space. IBM was the first to do this in the IBM AT.}} Many [[motherboard]]s enabled overclocking of these from the default 6 or 8&nbsp;MHz to perhaps 16.7 or 20&nbsp;MHz (half the i486 bus clock) in several steps, often from within the [[BIOS]] setup. Especially older peripheral cards normally worked well at such speeds as they often used standard MSI chips instead of slower (at the time) custom [[VLSI]] designs. This could give significant performance gains (such as for old video cards moved from a 386 or 286 computer, for example). However, operation beyond 8 or 10&nbsp;MHz could sometimes lead to stability problems, at least in systems equipped with [[SCSI]] or [[sound cards]].
Some motherboards came equipped with a [[32-bit computing|32-bit]] EISA bus that was backward compatible with the ISA-standard. EISA offered attractive features such as increased bandwidth, extended addressing, IRQ sharing, and card configuration through software (rather than through jumpers, DIP switches, etc.) However, EISA cards were expensive and therefore mostly employed in servers and workstations. Consumer desktops often used the simpler, faster [[VESA Local Bus]] (VLB). Unfortunately prone to electrical and timing-based instability; typical consumer desktops had ISA slots combined with a single VLB slot for a video card. VLB was gradually replaced by [[Peripheral Component Interconnect|PCI]] during the final years of the i486 period. Few [[Pentium class]] motherboards had VLB support as VLB was based directly on the i486 bus; much different from the P5 Pentium-bus. ISA persisted through the P5 Pentium generation and was not completely displaced by PCI until the Pentium III era, although ISA persisted well into the Pentium 4 era, especially among industrial PCs.
Late i486 boards were normally equipped with both PCI and ISA slots, and sometimes a single VLB slot. In this configuration, VLB or PCI throughput suffered depending on how buses were bridged. Initially, the VLB slot in these systems was usually fully compatible only with video cards (fitting as "VESA" stands for ''[[VESA|Video Electronics Standards Association]]''); VLB-IDE, multi I/O, or SCSI cards could have problems on motherboards with PCI slots. The VL-Bus operated at the same clock speed as the i486-bus (basically a local bus) while the PCI bus also usually depended on the i486 clock but sometimes had a divider setting available via the BIOS. This could be set to 1/1 or 1/2, sometimes even 2/3 (for 50&nbsp;MHz CPU clocks). Some motherboards limited the PCI clock to the specified maximum of 33&nbsp;MHz and certain network cards depended on this frequency for correct bit-rates. The ISA clock was typically generated by a divider of the CPU/VLB/PCI clock.
One of the earliest complete systems to use the i486 chip was the Apricot VX FT, produced by British hardware manufacturer [[Apricot Computers]].<ref name="byte198909_apricot">{{ cite magazine | url=https://archive.org/details/eu_BYTE-1989-09_OCR/page/n162/mode/1up | title=The 486s Are Here | magazine=Byte | date=September 1989 | access-date=30 April 2022 | last1=Lavin | first1=Paul | last2=Nadeau | first2=Michael E. | pages=95–98 }}</ref> Even overseas in the United States it was popularized as "The World's First 486".
Later i486 boards supported [[Plug-And-Play]], a specification designed by [[Microsoft]] that began as a part of [[Windows 95]] to make component installation easier for consumers.
==Obsolescence==
The [[AMD Am5x86]] and [[Cyrix Cx5x86]] were the last i486 processors often used in late-generation i486 motherboards. They came with PCI slots and 72-pin SIMMs that were designed to run [[Windows 95]], and also used for 80486 motherboards upgrades. While the [[Cyrix Cx5x86]] faded when the [[Cyrix 6x86]] took over, the [[AMD Am5x86]] remained important given [[AMD K5]] delays.
Computers based on the i486 remained popular through the late 1990s, serving as low-end processors for entry-level PCs. Production for traditional desktop and laptop systems ceased in 1998, when Intel introduced the [[Celeron]] brand, though it continued to be produced for [[embedded systems]] through the late 2000s.
In the general-purpose desktop computer role, i486-based machines remained in use into the early 2000s, especially as Windows 95 through [[Windows 98|98]] and [[Windows NT 4.0]] were the last Microsoft operating systems to officially support i486-based systems.<ref>{{cite web |url = http://support.microsoft.com/kb/182751 |title = Minimum Hardware Requirements for a Windows 98 Installation |date = January 24, 2001 |archive-url = https://web.archive.org/web/20041205061101/http://support.microsoft.com/kb/182751 |archive-date = December 5, 2004 }}</ref><ref>{{cite web |url = http://www.winhistory.de/more/nt4.htm |title = Windows NT 4.0 Workstation |publisher = WinHistory.de |language=de}}</ref> [[Windows 2000]] could run on a i486-based machine, although with a less than optimal performance, due to the minimum hardware requirement of a Pentium processor.<ref>{{cite web |url = https://www.youtube.com/watch?v=d33rIWdgc_A&t=380s&ab_channel=HARDWARECOP |title = World Record*: Windows 2000 running on Intel i486 SX 25 MHz |website = [[YouTube]] |date = July 29, 2013 }}</ref> However, as they were overtaken by newer operating systems, i486 systems fell out of use except for [[backward compatibility]] with older programs (most notably games), especially given problems running on newer operating systems. However, [[DOSBox]] was available for later operating systems and provides emulation of the i486 instruction set, as well as full compatibility with most DOS-based programs.<ref>{{cite web |url = http://www.dosbox.com/wiki/System_Requirements |title = System Requirements |publisher = DOSBox.com }}</ref>
The i486 was eventually overtaken by the Pentium for [[personal computer]] applications, although Intel continued production for use in [[embedded systems]]. In May 2006, Intel announced that production of the i486 would stop at the end of September 2007.<ref name="i486LastShipment2007"/><ref>{{cite web |url = http://www.reghardware.co.uk/2006/05/18/intel_cans_386_486_960_cpus/ |title = Intel cashes in ancient chips. i386, i486, i960 finally for the chop |date = May 18, 2006 |author = Tony Smith |access-date = May 20, 2012 |publisher = [[The Register]] Hardware |archive-url = https://web.archive.org/web/20110813073335/http://www.reghardware.com/2006/05/18/intel_cans_386_486_960_cpus/ |archive-date = August 13, 2011 |url-status = dead }}</ref>
==See also==
*[[List of Intel microprocessors]]
*[[Motorola 68040]], although not compatible, was often positioned as the [[Motorola]] equivalent to the Intel 486 in terms of performance and features.
*VL86C020, [[ARM3]] core of similar time frame and comparable MIPS performance on integer code (25&nbsp;MHz for both), with 310,000 transistors (in a 1.5&nbsp;μm process) instead of 1 million
== Notes ==
{{Notelist}}
== Further reading ==
*{{Cite web |last=Gamer |first=Brassic |date=2023-01-01 |title=The Brassic Gamer: The (Almost) Definitive 486DX/50 Article |url=https://brassicgamer.blogspot.com/2023/01/the-almost-definitive-486dx50-article.html |access-date=2023-01-03 |website=The Brassic Gamer}}
==References==
{{Reflist}}
==External links==
* [http://datasheets.chipdb.org/Intel/x86/486/datashts Intel486 datasheets]
** [http://datasheets.chipdb.org/Intel/x86/486/datashts/241199-002.pdf Low power SX and DX with variable freq. Dec 1992]
** [http://datasheets.chipdb.org/Intel/x86/486/datashts/27273102.PDF EMBEDDED ULTRA-LOW POWER Intel 486 SX]
** [http://datasheets.chipdb.org/Intel/x86/486/datashts/27277101.pdf Embedded Write-Back Enhanced Intel DX4. Oct 1995]
* [http://www.cpu-collection.de/?l0=co&l1=Intel&l2=i486%20DX Intel i486 DX images and descriptions at cpu-collection.de]
* [http://download.intel.com/newsroom/kits/40thanniversary/gallery/images/80486_die.jpg Die photo of Intel 386DX]
{{Intel processors|discontinued}}
{{Authority control}}
{{DEFAULTSORT:Intel I486}}
[[Category:Intel x86 microprocessors|80486]]<!--For the sake of sorting within category-->
[[Category:32-bit microprocessors]]
[[Category:Computer-related introductions in 1989]]
[[Category:X86 microarchitectures]]