View source for X87

{{lowercase}}
{{short description|Subset of x86 instruction set architecture for floating-point arithmetic}}
'''x87''' is a [[floating-point]]-related subset of the [[x86 architecture]] [[instruction set]]. It originated as an extension of the [[8086]] instruction set in the form of optional floating-point [[coprocessor#Intel coprocessors|coprocessors]] that work in tandem with corresponding x86 CPUs. These microchips have names ending in "87". This is also known as the NPX (numeric processor extension). Like other extensions to the basic instruction set, x87 instructions are not strictly needed to construct working programs, but provide hardware and [[microcode]] implementations of common numerical tasks, allowing these tasks to be performed much faster than corresponding [[machine code]] routines can. The x87 instruction set includes instructions for basic floating-point operations such as addition, subtraction and comparison, but also for more complex numerical operations, such as the computation of the [[trigonometric functions|tangent]] function and its inverse, for example.
Most x86 processors since the [[Intel 80486]] have had these x87 instructions implemented in the main CPU, but the term is sometimes still used to refer to that part of the instruction set. Before x87 instructions were standard in PCs, [[compiler]]s or programmers had to use rather slow library calls to perform floating-point operations, a method that is still common in (low-cost) [[embedded system]]s.
==Description==
The x87 registers form an eight-level deep non-strict [[stack (abstract data type)|stack]] structure ranging from ST(0) to ST(7) with registers that can be directly accessed by either operand, using an offset relative to the top, as well as pushed and popped. (This scheme may be compared to how a [[stack frame]] may be both pushed/popped and indexed.)
There are instructions to push, calculate, and pop values on top of this stack; [[unary operation]]s (FSQRT, FPTAN etc.) then implicitly address the topmost ST(0), while [[binary function|binary operations]] (FADD, FMUL, FCOM, etc.) implicitly address ST(0) and ST(1). The non-strict stack model also allows binary operations to use ST(0) together with a direct ''[[operand#Computer science|memory operand]]'' or with an ''explicitly'' specified stack register, ST(''x''), in a role similar to a traditional [[accumulator (computing)|accumulator]] (a combined destination and left operand). This can also be reversed on an instruction-by-instruction basis with ST(0) as the unmodified operand and ST(''x'') as the ''destination''. Furthermore, the contents in ST(0) can be exchanged with another stack register using an instruction called FXCH ST(''x'').
These properties make the x87 stack usable as seven freely addressable registers plus a dedicated accumulator (or as seven independent accumulators). This is especially applicable on [[superscalar]] x86 processors (such as the [[Intel P5 (microarchitecture)|Pentium]] of 1993 and later), where these exchange instructions (codes D9C8..D9CF<sub>h</sub>) are optimized down to a zero clock penalty by using one of the integer paths for FXCH ST(''x'') in parallel with the FPU instruction. Despite being natural and convenient for human [[assembly language]] programmers, some compiler writers have found it complicated to construct automatic [[code generation (compiler)|code generators]] that schedule x87 code effectively. Such a stack-based interface potentially can minimize the need to save scratch variables in function calls compared with a register-based interface<ref name=stackadvantage>{{cite web |url=http://www.cims.nyu.edu/~dbindel/class/cs279/87stack.pdf | title=On the advantages of 8087's stack|archive-url=https://web.archive.org/web/20170118054747/http://www.cims.nyu.edu/~dbindel/class/cs279/87stack.pdf|archive-date=18 January 2017|url-status=dead|work=Unpublished course notes, Computer Science Division, University of California at Berkeley | author=William Kahan |date=2 November 1990}}</ref> (although, historically, design issues in the 8087 implementation limited that potential.<ref name=stackimplementation>{{cite web |url=http://www.cims.nyu.edu/~dbindel/class/cs279/stack87.pdf | title=How Intel 8087 stack overflow/underflow should have been handled | author=William Kahan |date=8 July 1989 |archive-url=https://web.archive.org/web/20130612040231/http://www.cims.nyu.edu/~dbindel/class/cs279/stack87.pdf |archive-date=12 June 2013 |url-status=dead}}</ref><ref name=stackinterview>{{cite web |url=https://drdobbs.com/architecture-and-design/a-conversation-with-william-kahan/184410314 | title=A conversation with William Kahan | author=Jack Woehr |date=1 November 1997}}</ref>)
The x87 provides single-precision, double-precision and 80-bit [[extended precision|double-extended precision]] binary floating-point arithmetic as per the [[IEEE 754-1985]] standard. By default, the x87 processors all use 80-bit double-extended precision internally (to allow sustained precision over many calculations, see [[IEEE_754#Design_rationale|IEEE 754 design rationale]]). A given sequence of arithmetic operations may thus behave slightly differently compared to a strict single-precision or double-precision IEEE 754 FPU.<ref>{{cite journal |author=David Monniaux |url=https://dl.acm.org/doi/pdf/10.1145/1353445.1353446 |title=The pitfalls of verifying floating-point computations |journal=[[ACM Transactions on Programming Languages and Systems]] |volume=30 |issue=3 |date=May 2008 |pages=1–41 |doi=10.1145/1353445.1353446|arxiv=cs/0701192 |s2cid=218578808 }}</ref> As this may sometimes be problematic for some semi-numerical calculations written to assume double precision for correct operation, to avoid such problems, the x87 can be configured using a special configuration/status register to automatically round to single or double precision after each operation. Since the introduction of [[SSE2]], the x87 instructions are not as essential as they once were, but remain important as a high-precision scalar unit for numerical calculations sensitive to [[round-off error]] and requiring the [[64-bit]] [[significand|mantissa]] [[Arithmetic precision|precision]] and extended range available in the 80-bit format.
===Performance===
Clock cycle counts for examples of typical x87 FPU instructions (only register-register versions shown here).<ref>Numbers are taken from respective processors' data sheets, programming manuals, and optimization manuals.</ref>
The ''A''...''B'' notation (minimum to maximum) covers timing variations dependent on transient pipeline status and the arithmetic precision chosen (32, 64 or 80 bits); it also includes variations due to numerical cases (such as the number of set bits, zero, etc.). The L → H notation depicts values corresponding to the lowest (L) and the highest (H) maximal clock frequencies that were available.
{| class="wikitable"
|-
! x87 implementation
! FADD
! FMUL
! FDIV
! FXCH
! FCOM
! FSQRT
! FPTAN
! FPATAN
! Max clock<br>(MHz)
! Peak FMUL<br>(millions/[[second|s]])
! FMUL<sup>§</sup><br>rel. 5&nbsp;MHz 8087
|-
| 8087                                                   || rowspan="2" | 70…100 || rowspan="2" | 90…145 || rowspan="2" | 193…203 || rowspan="2" | 10…15 || rowspan="2" | 40…50 || rowspan="2" | 180…186 || rowspan="2" | 30…540  || rowspan="2" | 250…800 || {{0|000}}5 → {{0|00}}10  || 0.034…0.055 → 0.100…0.111 || {{0|~0000}}1 → 2× as fast
|-
| 80287 (original)                                                                                                                         || {{0|000}}6 → {{0|00}}12  || 0.041…0.066 → 0.083…0.133     || {{0|.000}}1.2 → 2.4×
|-
| 80387 (and later 287 models)                           || 23…34  || 29…57  || 88…91   || 18    || 24    || 122…129 || 191…497 || 314…487 || {{0|00}}16 → {{0|00}}33  || 0.280…0.552 → 0.580…1.1 || {{0|000}}~10 → 20×
|-
| [[80486]] (or 80487)                                   || 8…20   || 16     || 73      || 4     || 4     || 83…87   || 200…273 || 218…303 || {{0|00}}16 → {{0|00}}50  || {{0|….000000}}1.0 → 3.1 || {{0|000}}~18 → 56×
|-
| [[Cyrix 6x86]], [[Cyrix MII]]                          || 4…7    || 4…6    || 24…34   || 2     || 4     || 59…60   || 117…129 || 97…161  || {{0|00}}66 → {{0}}300 || {{0|..0000}}11…16 → 50…75 || {{0|00}}~320 → 1400×
|-
| [[AMD K6]] (including K6 II/III)                       || 2      || 2      || 21…41   || 2     || 3     || 21…41   || ?       || ?       || {{0}}166 → {{0}}550   || {{0|…..000000}}83 → 275 || {{0}}~1500 → 5000×
|-
| [[Intel P5 (microarchitecture)|Pentium]] / Pentium MMX || 1…3    || 1…3    || 39      || rowspan="5" | 1 (0*)
| 1…4   || 70      || 17…173  || 19…134  || {{0|00}}60 → {{0}}300 || {{0|..0000}}20…60 → 100…300 || {{0}}~1100 → 5400×
|-
| [[Pentium Pro]]                                        || 1…3    || 2…5    || 16…56            || 1     || 28…68   || ?       || ?       || {{0}}150 → {{0}}200   || {{0|..0000}}30…75 → 40…100 || {{0}}~1400 → 1800×
|-
| [[Pentium II]] / III                                   || 1…3    || 2…5    || 17…38            || 1     || 27…50   || ?       || ?       || {{0}}233 → 1400  || {{0|..000}}47…116 → 280…700 || {{0}}~2100 → 13000×
|-
| [[Athlon]] (K7)                                        || rowspan="2 | 1…4    || rowspan="2 | 1…4    || rowspan="2 | 13…24            || rowspan="2 | 1…2   || rowspan="2 | 16…35   || rowspan="2 | ?       || rowspan="2 | ?       || {{0}}500 → 2330  || {{0|..00}}125…500 → 580…2330 || {{0}}~9000 → 42000×
|-
| [[Athlon 64]] (K8)                                                                                                                       || 1000 → 3200      || {{0|..0}}250…1000 → 800…3200 || ~18000 → 58000×
|- style="vertical-align:top;"
| [[Pentium 4]]                                          || 1…5    || 2…7    || 20…43            || multiple<br>cycles ||1 ||20…43 || ? || ? || 1300 → 3800    || {{0|..00}}186…650 → 543…1900 || ~11000 → 34000×
|}
:<small>* An effective zero clock delay is often possible, via superscalar execution.</small>
:<small><sup>§</sup> The 5&nbsp;MHz 8087 was the original x87 processor. Compared to typical software-implemented floating-point routines on an 8086 (without an 8087), the factors would be even larger, perhaps by another factor of 10 (i.e., a correct floating-point addition in assembly language may well consume over 1000 cycles).</small>
==Manufacturers==
Companies that have designed or manufactured{{Efn|[[Fabless]] companies design a chip and rely on a fabbed company to manufacture it, while fabbed companies can do both the design and the manufacture by themselves.}} floating-point units compatible with the Intel 8087 or later models include [[AMD]] (''287'', ''387'', ''486DX'', ''5x86'', ''K5'', ''K6'', ''K7'', ''K8''), [[Chips and Technologies]] (the ''Super MATH'' coprocessors), [[Cyrix]] (the ''FasMath'', ''Cx87SLC'', ''Cx87DLC'', etc., ''6x86'', ''Cyrix MII''), [[Fujitsu]] (early ''Pentium Mobile'' etc.), [[Harris Semiconductor]] (manufactured ''80387'' and ''486DX'' processors), [[IBM]] (various ''387'' and ''486'' designs), [[Integrated Device Technology|IDT]] (the [[WinChip]], ''C3'', ''C7'', ''Nano'', etc.), [[Integrated Information Technology|IIT]] (the ''2C87'', ''3C87'', etc.), LC Technology (the ''Green MATH'' coprocessors), [[National Semiconductor]] (the ''Geode GX1'', ''Geode GXm'', etc.), [[NexGen]] (the ''Nx587''), [[Rise Technology]] (the ''mP6''), [[ST Microelectronics]] (manufactured ''486DX'', ''5x86'', etc.), [[Texas Instruments]] (manufactured ''486DX'' processors etc.), [[Transmeta]] (the ''TM5600'' and ''TM5800''), [[ULSI]] (the ''Math·Co'' coprocessors), [[VIA Technologies|VIA]] (the ''C3'', ''C7'', and ''Nano'', etc.), [[Weitek]] (the ''1067'', ''1167'', ''3167'' and ''4167''), and Xtend (the ''83S87SX-25'' and other coprocessors).
==Architectural generations==
===8087===
{{Main|Intel 8087}}
The ''8087'' was the first math [[coprocessor]] for 16-bit processors designed by [[Intel]]. It was built to be paired with the [[Intel 8088]] or [[Intel 8086|8086]] microprocessors. (Intel's earlier [[Intel 8231/8232|8231 and 8232]] floating-point processors, marketed for use with the i8080 CPU, were in fact licensed versions of AMD's Am9511 and Am9512 FPUs from 1977 and 1979.<ref>{{cite web|url=https://www.cpushack.com/2010/09/23/arithmetic-processors-then-and-now/|title=Arithmetic Processors: Then and Now |website=www.cpushack.com|date=23 September 2010 |access-date=3 May 2023}}</ref>)
===80C187{{anchor|80187}}===
[[Image:KL Intel 80C187.jpg|right|thumb|150px|16 MHz version of the Intel 80C187]]
Although the original 1982 datasheet for the ([[NMOS logic|NMOS]] based) 80188 and 80186 seem to mention specific math coprocessors,<ref>{{Cite book |last=Intel |url=http://archive.org/details/IntelMicroprocessorPeripheralsHandbook |title=Intel Microprocessor & Peripherals Handbook |date=1983 |pages=3-25 (iAPX 186/20) and 3-106 (iAPX 188/20)}}</ref> both chips were actually paired with an 8087.
However, in 1987, to work with the refreshed [[CMOS]] based [[Intel 80186#80C186|Intel 80C186]] CPU, Intel introduced the '''80C187'''<ref>{{cite web |title=CPU Collection – Model 80187 |url=http://www.cpu-info.com/index2.php?mainid=Overview&showm=8 |url-status=dead |archive-url=https://web.archive.org/web/20110723142209/http://www.cpu-info.com/index2.php?mainid=Overview&showm=8 |archive-date=23 July 2011 |access-date=14 April 2018 |website=cpu-info.com}}</ref> math coprocessor.  The 80C187 interface to the main processor is the same as that of the 8087, but its core is essentially that of an 80387SX and is thus fully [[IEEE 754-1985|IEEE 754]]-compliant and capable of executing all the 80387's extra instructions.<ref>{{cite web |url=https://nj7p.org/Manuals/PDFs/Intel/270640-004.pdf |title=80C187 80-BIT MATH COPROCESSOR |date=November 1992 |access-date=3 May 2023}}</ref>
===80287===
The ''80287'' (''i287'') is the math [[coprocessor]] for the [[Intel 80286]] series of [[microprocessor]]s. Intel's models included variants with specified upper frequency limits ranging from 6 up to 12&nbsp;MHz. The NMOS version were available 6, 8 and 10 MHz.<ref>Yoshida, Stacy, "Math Coprocessors: Keeping Your Computer Up for the Count", Intel Corporation, Microcomputer Solutions, September/October 1990, page 16</ref>  The available 10&nbsp;MHz Intel 80287-10 Numerics Coprocessor version was for 250&nbsp;[[USD]] in quantities of 100.<ref>Intel Corporation, "New Product Focus Component: A 32-Bit Microprocessor With A Little Help From Some Friends", Special 32-Bit Issue Solutions, November/December 1985, page 13.</ref>  These boxed version of 80287, 80287-8, and 80287-10 were available for USD $212, $326, and $374 respectively.  There was boxed version of 80C287A available for USD $457.<ref>[https://archive.org/details/19891101ipcep Intel Corporation, "Personal Computer Enhancement", Personal Computer Enhancement Operation, Order No. 245.2, 10-89/75K/AL/GO, October 1989, page 4]</ref>  Other 287 models with 387-like performance are the Intel 80C287, built using [[CHMOS]] III, and the AMD 80EC287 manufactured in AMD's [[CMOS]] process, using only fully static gates.
Later followed the i80287XL with 387SX microarchitecture with a 287 pinout,<ref>Intel Corporation, "New Product Focus: Systems: SnapIn 386 Module Upgrades PS/2 PCs", Microcomputer Solutions, September/October 1991, page 12</ref> the i80287XLT, a special version intended for laptops, as well as other variants. It contains an internal 3/2 multiplier, so that motherboards that ran the coprocessor at 2/3 CPU speed could instead run the FPU at the same speed of the CPU.  Both 80287XL and 80287XLT offered 50% better performance, 83% less power consumption, and additional instructions.<ref>Yoshida, Stacy, "Math Coprocessors: Keeping Your Computer Up for the Count", Intel Corporation, Microcomputer Solutions, September/October 1990, page 16</ref>
The 80287 works with the [[80386]] microprocessor and was initially the only coprocessor available for the 80386 until the introduction of the 80387 in 1987. However, the 80387 is strongly preferred for its higher performance and the greater capability of its instruction set.
<gallery>
KL Intel C80287.jpg|6 MHz version of the Intel 80287
Intel 80287 die.jpg|Intel 80287 die shot
KL Intel i80287XL Big Markings.jpg|Intel 80287XL
KL Intel 80287XLT.jpg|Intel 80287XLT
</gallery>
===80387===
[[File:Intel 80387 CPU Die Image.jpg|thumb|Intel 80387 CPU die image]]
The '''80387''' ('''387''' or '''i387''') is the first Intel coprocessor to be fully compliant with the [[IEEE 754-1985]] standard. Released in 1987,<ref name="InfoWorld 1987-02-16">{{cite magazine|magazine=[[InfoWorld]]|date=1987-02-16|df=ymd|last=Moran|first=Tom|title=Chips to Improve Performance Of 386 Machines, Intel Says|volume=9|issue=7|page=5|issn=0199-6649|language=en-us|url=https://books.google.com/books?id=0DAEAAAAMBAJ&pg=PA5}}</ref> two years after the 386 chip, the i387 includes much improved speed over Intel's previous 8087/80287 coprocessors and improved characteristics of its trigonometric functions. It was made available for USD $500 in quantities of 100.<ref>{{cite journal|publisher=Intel Corporation|title=New Product Focus Components: The 32-Bit Computing Engine Full Speed Ahead|journal=Solutions|date=May–June 1987|page=10}}</ref> Shortly afterwards, it was made available through Intel's Personal Computer Enhancement Operation for a retail market price of USD $795.<ref>{{cite journal|publisher=Intel Corporation|title=NewsBit: Intel 80387 Available Through Retail Channels|journal=Solutions|date=July–August 1987|page=1}}</ref> The 25 MHz version was available in retail channel for USD $1395.<ref>Intel Corporation, "NewsBits: 25 MHZ 80387 Available Through Retail Channels", Microcomputer Solutions, September/October 1988, page 1</ref> The Intel M387 math coprocessor met under [[MIL-STD-883|MIL-STD-883 Rev. C standard]].  This device was tested which includes temperature cycling between -55 and 125 °C, hermeticity sealed and extended burn-in.  This military version operates at 16 MHz.  This military version was available in 68-lead PGA and quad flatpack.  This military version was available for USD $1155 in 100-unit of quantities for the PGA version.<ref>Intel Corporation, "Focus: Components: Militarized Peripherals Support M386 Microprocessor", Microcomputer Solutions, March/April 1989, page 12</ref>  The 33 MHz version of 387DX was available and it has the performance of 3.4 [[Whetstone (benchmark)|megawhetstones per second]].<ref>Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2</ref> The following boxed version of 16-, 20-, 25-, and 33-MHz 387DX math coprocessor were available for USD $570, $647, $814, and $994 respectfully.<ref>[https://archive.org/details/19891101ipcep Intel Corporation, "Personal Computer Enhancement", Personal Computer Enhancement Operation, Order No. 245.2, 10-89/75K/AL/GO, October 1989]</ref> The 8087 and 80287's FPTAN and FPATAN instructions are limited to an argument in the range ±π/4 (±45°), and the 8087 and 80287 have no ''direct'' instructions for the SIN and COS functions.<ref>Borland Turbo Assembler documentation.</ref>{{Full citation needed|date=August 2020}}
Without a coprocessor, the 386 normally performs floating-point arithmetic through (relatively slow) software routines, implemented at runtime through a software [[Exception handling|exception handler]]. When a math coprocessor is paired with the 386, the coprocessor performs the floating-point arithmetic in hardware, returning results much faster than an (emulating) software library call.
The i387 is compatible only with the standard i386 chip, which has a 32-bit processor bus. The later cost-reduced i386SX, which has a narrower 16-bit [[Bus (computing)|data bus]], can not interface with the i387's 32-bit bus. The i386SX requires its own coprocessor, the [[80387SX]], which is compatible with the SX's narrower 16-bit data bus.  Intel released the low power version of 387SX coprocessor.<ref>Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2</ref>
There was an Intel387 SL Mobile Math Coprocessor that has power-management features which can run without significantly reducing battery life.  There are two battery-saving power-down modes.  The first one contains "stop clock" mode which automatically shutting down the math coprocessor when it not needed.  This mode consumes about 25 microamperes.  The second mode operates automatically when the user is running application which requires the coprocessor is executing an instruction.  That mode typically consumes 30 percent less battery power (about 100 mA) than the regular Intel387 SX Math Coprocessor.  It goes to "idle" mode when it is not executing an instruction down to less than 4 mA a 96 percent power reduction compared to the active mode.  It will work in the range of 16 to 25 MHz and does not require BIOS or hardware reconfiguration.  It was available for USD $189.<ref>Intel Corporation, "New Product Focus: End-User: Math Coprocessor Brings Desktop Performance To Portables", Microcomputer Solutions, May/June 1992, page 16-17</ref>
<gallery>
File:KL Intel 80387.jpg|i387
File:KL Intel i387SX.jpg|i387SX
File:KL intel i387DX.jpg|i387DX
File:Intel 387 arch.svg|i387 microarchitecture with 16-bit [[barrel shifter]] and [[CORDIC]] unit
File:80386with387.JPG|i386DX with i387DX
File:Socket for Intel 80387.jpg|Socket for the 80387
</gallery>
===80487===
[[File:KL Intel i487SX.jpg|150px|thumb|i487SX]]
The '''i487SX''' (P23N) was marketed as a [[floating-point unit]] [[coprocessor]] for Intel [[Intel 80486SX|i486SX]] machines. It actually contained a full-blown [[486DX|i486DX]] implementation. When installed into an i486SX system, the i487 disabled the main CPU and took over all CPU operations. The i487 took measures to detect the presence of an i486SX and would not function without the original CPU in place.<ref>{{FOLDOC|Intel%20487SX|Intel 487SX|new=yes}}</ref><ref>{{Cite web|title=Intel 80487|url=https://www.cpu-world.com/CPUs/80487/index.html|access-date=2021-06-09|website=www.cpu-world.com}}</ref>{{Failed verification|date=July 2021}}
===80587===
The '''Nx587''' was the last FPU for x86 to be manufactured separately from the CPU, in this case NexGen's [[Nx586]].
==See also==
* [[MMX (instruction set)|MMX]]
* [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]]
* [[Advanced Vector Extensions|AVX]]
* [[3DNow!]]
* [[SIMD]]
==Notes==
{{Notelist}}
==References==
{{reflist}}
* {{cite book|url=https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|publisher=Intel|title=Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture}}
==External links==
* [https://web.archive.org/web/20180104181527/http://wiretap.area.com/Gopher/Library/Techdoc/Cpu/coproc.txt Everything you always wanted to know about math coprocessors]
{{Intel processors|discontinued}}
{{Use dmy dates|date=April 2019}}
[[Category:X86 architecture]]
[[Category:Floating point]]
[[Category:Computer-related introductions in 1980]]
[[Category:Coprocessors]]
[[Category:Stack machines]]